E2 series

E24

The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capabilities, implementing the RISC-V ISA’s F standard extension. The E24’s efficiency and floating-point capabilities make it exceptional at motor control, sensor fusion, and IoT applications.

E24
Key Features
  • RISC-V ISA - RV32IMAFC
    • Includes hardware single-precision floating-point support
  • Machine and User Mode with 4 Region Physical Memory Protection
  • 3-stage pipeline with Simultaneous Instruction and Data Access
  • 2 Banks of Tightly Integrated Memory
  • System, Peripheral, and Front Ports
  • CLIC interrupt controller with 127 interrupts
  • Advanced debug with 4 hardware breakpoints/watchpoints
  • 2.27/1.46 DMIPS/MHz (Best Effort/Legal)
  • 3.1 CoreMark/MHz
  • Detailed Power, Performance, and Area (PPA) Information
E2 Series
Cortex-M4F
Dhrystone Performance
1.46/2.27 DMIPS/MHza
1.95/1.25 DMIPS/MHz
CoreMark Performance with GCC
3.1 CoreMarks/MHzb
2.76 CoreMarks/MHz
Floating-Point Unit
Optional
Optional
Memory Map
Customizable
Fixed ARMv7-M
Interrupts
Up to 1024 interrupts
240 interrupts
Interrupt latency to C handler
6-cyclec
12-cycle
Memory Protection Regions
Up to 8 (optional)
0 or 8
Tightly Integrated Memory
2 Banks of TIM (optional)
None

a. E24 Standard Core Configuration, with GCC. The first score is using legal dhrystone compiler flags. The second score uses function inlining and link time optimizations.

b. E24 Standard Core Configuration, with GCC

c. CLIC Vectored Mode

E24
Development Kit

Dev Kit Deliverables

  • RTL Evaluation
  • Test Bench RTL
  • Software Development Kit
  • FPGA Bitstream
  • Documentation
E2
Series Overview

E2 Series

The E2 Series is highly optimized for area and power while still offering class-leading performance. Targeted for microcontroller and embedded devices, the E2 Core can be configured to be as small as 13.5k gates with an efficient 2‑stage pipeline or configured for higher performance with a 3‑stage pipeline, hardware floating-point, instruction cache, and more.

With SiFive Core Designer, the E2 Series can be fully customized to meet your specific requirements.

E2 Series
Highlights

Key Features

  • Configurable core performance
  • Single precision Floating Point Unit
  • Custom memory map and ports
  • Optional Tightly Integrated Memory (TIM)
  • RV32E support with the smallest core configuration as small as 13.5k gates and is .005mm2 in 28nm
  • SiFive Insight Advanced Trace and Debug

Applications

  • MEMS Sensors
  • Power managment
  • Digital motor control
  • Low-power MCUs
  • Health wearable monitors
  • Environmental monitors

All Standard
Cores

Area
Standard Cores
ARM Comparison
E2 Series
M0, M0+, M3, M4, M23, M33
E3 Series
R4, R5
E7 Series
M7, R7, R8
S2 Series
***
S5 Series
R4, R5
S7 Series
M7, R7, R8
U5 Series
A5, A7, A35, A53
U7 Series
A55
VIU7 Series
A55
U8 Series
A72, A73
Core Evaluation

From idea
to reality.

Ready to see your code in action? The E24 Development Kit enables free evaluation of SiFive RISC-V Core IP.

Key
Deliverables

Evaluation RTL

  • Full-Functional, synthesizable Verilog RTL
  • Run it in your own simulator
  • Simple, no-cost evaluation license
Start E24 Free Trial

FPGA Bitstream

  • Fully-functional SiFive RISC-V Core Complex with system peripherals
  • High Performance - 32.5 MHz emulation
  • Upload your own programs using the Freedom E SDK

Compatible with the Arty A7-100T and Xilinx VCU 118 FPGA Development Boards: