E2 series


The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capabilities by implementing the RISC-V ISA’s F standard extension. The E24’s efficiency, coupled with hardware floating-point capabilities, make it exceptional at motor control, sensor fusion, and IoT applications.

Key Features
    • Includes hardware single-precision floating-point support
  • Machine and User Mode with 4 Region Physical Memory Protection
  • 3-stage pipeline with Simultaneous Instruction and Data Access
  • 2 Banks of Tightly Integrated Memory
  • System, Peripheral, and Front Ports
  • CLIC interrupt controller with 127 interrupts
  • Advanced debug with 4 hardware breakpoints/watchpoints

Power, Performance, and Area

28nm HPC
55nm LP
Core-only Areaa
0.028 mm²
0.083 mm²
Core Complex Areab
0.049 mm²
0.14 mm²
585 MHz (worst)
210 MHz (worst)
Core Complex Powerc
1.54 mW
3.39 mW

Note: Area and power numbers do not include RAMs. Area numbers are from 50MHz Post-Route at worst setup corner.

a. Core only includes the core pipeline only

b. Core Complex includes the Core plus CLIC w/127 irq and 4 priority bits, Debug w/ 4 hw breakpoints, 4 Region PMP, TIM Logic, internal bus and AHB-Lite ports

c. Dhyrstone @ 50MHz TT Vnom 25C

Compare to Cortex-M4F

E2 Series
Dhrystone Performance
1.38 DMIPS/MHza
1.25 DMIPS/MHz
CoreMark Performance with GCC
3.1 CoreMarks/MHza
2.76 CoreMarks/MHz
Floating-Point Unit
Memory Map
Fixed ARMv7-M
Up to 1024 interrupts
240 interrupts
Interrupt latency to C handler
Memory Protection Regions
Up to 8 (optional)
0 or 8
Tightly Integrated Memory
2 Banks of TIM (optional)

a. E24 Standard Core Configuration, with GCC

b. CLIC Vectored Mode

Development Kit

Dev Kit Deliverables

  • RTL Evaluation
  • Test Bench RTL
  • Software Development Kit
  • FPGA Bitstream
  • Documentation
Series Overview

E2 Series

The E2 Series is highly-optimized for area and power while still offering class-leading performance. Targeted for microcontroller and embedded devices, the E2 Core can be configured to have an efficient 2‑stage pipeline or a higher performance 3‑stage pipeline as well as a Core Local Interrupt Controller (CLIC) enabling extremely fast interrupt response. The E2 Series can be fully customized to meet your specific requirements. Using the SiFive Core Designer the smallest possible E2 core can be configured using 13.5k gates.

E2 Series

Key Features

  • Core performance
  • Single precision Floating Point Unit
  • Custom memory map and ports
  • Optional Tightly Integrated Memory (TIM)
  • Smallest core configuration uses 13.5k gates and is .005mm2 in 28nm


  • MEMS Sensors
  • Power managment
  • Digital motor control
  • Low-power MCUs
  • Health wearable monitors
  • Environmental monitors

All Standard

Standard Cores
ARM Comparison
E2 Series
M0, M0+, M3, M4, M23, M33
E3 Series
R4, R5
E7 Series
M7, R7, R8
S2 Series
S5 Series
R4, R5
S7 Series
M7, R7, R8
U5 Series
A5, A7, A35, A53
U7 Series
Core Evaluation

From idea
to reality.

Ready to see your code in action? The E24 Development Kit enables free evaluation of SiFive RISC-V Core IP.


Evaluation RTL

  • Full-Functional, synthesizable Verilog RTL
  • Run it in your own simulator
  • Simple, no-cost evaluation license
Start E24 Free Trial

FPGA Bitstream

  • Fully-functional SiFive RISC-V Core Complex with system peripherals
  • High Performance - 65 MHz emulation
  • Upload your own programs using the Freedom E SDK

Compatible with the Arty A7 FPGA Development Board: