E3 series

E31

The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications.

E31
Key Features
  • Fully compliant with the RISC-V ISA specification
  • RV32IMAC Support
    • RV32I – 32-bit RISC-V with 32 integer registers
    • Integer Multiplication and Division (M) support
    • Atomic Mode (A) support for high-performance, portable software
    • Compressed Mode (C) support for better code density
  • Machine and User Mode Support
  • In-order, 5-6 stage variable pipeline
  • Advanced Memory Subsystem
    • 16KB, 2-way Instruction Cache
    • Instruction Tightly Integrated Memory (ITIM) option
    • Up to 64KB Data Tightly Integrated Memory (DTIM) support
  • Efficient and Flexible Interrupts
    • Local interrupts w/ vectored addresses — up to 16
    • Platform Level Interrupt Controller (PLIC) — 128 interrupts w/ 7 priority levels
    • RISC-V Core Local Interruptor (CLINT) — 1 timer, 1 SW
  • 8-Region Physical Memory Protection (PMP)
  • High performance AMBA Interfaces
  • 2.58/1.64 DMIPS/MHz (Best Effort/Legal)
  • 3.17 CoreMark/MHz
  • Detailed Power, Performance, and Area (PPA) Information
E3 Series
Cortex-R5
Architecture
32-bit
32-bit
Cores
Up to 8 Cores (fully-coherent)
Up to 2 Cores (non-coherent)
Interrupt Controller
Included; pre-integrated
Licensed separately; requires integration
L2 Cache Controller
Included (optional); pre-integrated
Licensed separately; requires integration

E31
Development Kit

Dev Kit Deliverables

  • RTL Evaluation
  • Test Bench RTL
  • Software Development Kit
  • FPGA Bitstream
  • Documentation
E3
Series Overview

E3 Series

The E3 Series is highly-integrated and feature-rich. It includes the E31 Core, which is the most widely deployed RISC‑V core in the world. E3 embedded cores have a 5-6 stage pipeline, offering a great balance between performance and efficiency.

E3 Series
Highlights

Key Features

  • Up to 8 coherent E3 Cores and optional L2 Cache Controller
  • Configurable core performance
  • Optional Single or Double precision Floating Point Unit
  • Level 1 Memory System and ECC
  • Number, type, and width of bus interfaces
  • Support for SiFive Insight Advanced Trace and Debug

Applications

  • Consumer Electronics
  • Motor Control
  • Industrial Automation
  • Storage
  • High-performance embedded

SiFive Essential
Standard Cores

Area
Standard Cores
ARM Comparison
E2 Series
M0, M0+, M3, M4, M23, M33
E3 Series
R4, R5
E6 Series
M0, M0+, M3, M4, M23, M33
E7 Series
M7, R7, R8
S2 Series
***
S5 Series
R4, R5
S6 Series
***
S7 Series
M7, R7, R8
U5 Series
A5, A7, A35, A53
U6 Series
***
U7 Series
A55
Core Evaluation

From idea
to reality.

Ready to see your code in action? The E31 Development Kit enables free evaluation of SiFive RISC-V Core IP.

Key
Deliverables

Evaluation RTL

  • Full-Functional, synthesizable Verilog RTL
  • Run it in your own simulator
  • Simple, no-cost evaluation license
Start E31 Free Trial

FPGA Bitstream

  • Fully-functional SiFive RISC-V Core Complex with system peripherals
  • High Performance - 32.5 MHz emulation
  • Upload your own programs using the Freedom E SDK

Compatible with the Arty A7-100T and Xilinx VCU118 FPGA Development Boards: