SiFive Performance

SiFive Performance P550

The SiFive Performance P550 features a thirteen-stage, triple-issue, out-of-order pipeline compatible with the RISC-V RV64GBC ISA. Evolved from the previously announced SiFive U84 microarchitecture, Performance P550 scales up to four-core complex configurations that use a similar amount of area as a single Arm Cortex-A75 while delivering a significant performance-per-area advantage.

SiFive Performance P550 Key Features
  • Breakthrough RISC-V performance
    • 3x Performance per mm2 compared to Cortex-A75
    • Performance >8.6 SpecINT2k6/GHz, Higher single threaded performance than Cortex-A75
  • P550 Core Architectural Features
    • RV64GBC capable core with Sv39/Sv48 Virtual Memory Support
    • Three Issue, out-of-order Pipeline tuned for scalable performance
    • Private L2 Caches and Streaming Prefetcher for improved memory performance
    • SECDED ECC with Error Reporting
  • Enabling next generation applications
    • Cache stashing to L3 for tightly coupled accelerators
    • Mix+Match capable for real-time deterministic workloads

Performance P550 Development Kit

Dev Kit Deliverables

  • RTL Evaluation
  • Test Bench RTL
  • Software Development Kit
  • FPGA Bitstream
  • Documentation
Core Evaluation

From idea to reality.

Ready to see your code in action? The SiFive Performance P550 Development Kit enables evaluation of SiFive RISC-V Core IP.

Key Deliverables

Evaluation RTL

  • Full-Functional, synthesizable Verilog RTL
  • Run it in your own simulator
Accepting Lead Partners Now