S2 Series


The SiFive S21 Standard Core is a full-featured 64-bit embedded processor based on the S2 Series. The S21 has separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs). The S21 is an ideal choice for area constrained applications demanding a 64-bit processor.

S21 Key Features

  • 64-bit AXI Ports
  • Machine and User Mode with 4 Region Physical Memory Protection
  • 3-stage pipeline with Simultaneous Instruction and Data Access
  • 2 Banks of Tightly Integrated Memory
  • CLIC interrupt controller with 127 interrupts
  • Advanced debug with 4 hardware breakpoints/watchpoints
  • 2.54/1.6 DMIPS/MHz (Best Effort/Legal)
  • 3.2 Coremarks/MHz
50 MHz
475 MHz
Core-Only Areab
0.035 mm²
0.061 mm²
Core-Only Dynamic Powerc
1.42 μW/MHz
Core-Complex Aread
0.072 mm²
0.109 mm²
Core-Complex Powere
0.811 mW

Note: Area and power numbers do not include RAMs and are Post-Route

a. Example Implementations; Area Optimized and Balanced. Frequency is reported at Worst 0.81v, -40°C

b. Core-Only includes the core pipeline and memory interfaces

c. Power is reported at Typical 0.9v, 25°C for Dhrystone

d. Core Complex includes the Core plus CLIC w/127 irq and 4 priority bits, Debug w/4 hw breakpoints, 4 Region PMP, TIM Logic, internal bus and ports

e. Core-Complex total power includes dynamic and leakage and is reported at Typical 0.9v, 25°C for Dhrystone

S2 Series
Instruction Set Architecture
Dhrystone Performance
1.6 DMIPS/MHza
CoreMark Performance with GCC
3.2 CoreMarks/MHza
Floating-Point Unit
Memory Map
Up to 1024
Interrupt latency to C handler
Memory Protection Regions
Up to 8 (optional)
Tightly Integrated Memory
2 Banks of TIM (optional)

a. S21 Standard Core Configuration, using GCC

b. CLIC Vectored Mode

S21 Development Kit

Dev Kit Deliverables

  • RTL Evaluation
  • Test Bench RTL
  • Software Development Kit
  • FPGA Bitstream
  • Documentation
Series Overview

S2 Series

The S2 Series is a 64-bit microcontroller highly-optimized for area, efficient performance, and simplified integration into 64-bit SoCs. The S2 core has the same efficient 2‑stage or 3-stage pipeline as the E2 Series as well as a Core Local Interrupt Controller (CLIC) enabling extremely fast interrupt response. The S2 Series can be fully customized to meet your specific requirements.

S2 Series Highlights

Key Features

  • 64-bit CPU
  • Greater than 32-bit physical address
  • Optional Tightly Integrated Memory (TIM)
  • Configurability


  • 64-bit Embedded Controller
  • Consumer
  • Industrial Automation
  • Management Core

All Standard Cores

Standard Cores
ARM Comparison
E2 Series
M0, M0+, M3, M4, M23, M33
E3 Series
R4, R5
E7 Series
M7, R7, R8
S2 Series
S5 Series
R4, R5
S7 Series
M7, R7, R8
U5 Series
A5, A7, A35, A53
U7 Series
Core Evaluation

From idea to reality.

Ready to see your code in action? The S21 Development Kit enables free evaluation of SiFive RISC-V Core IP.


Evaluation RTL

  • Full-Functional, synthesizable Verilog RTL
  • Run it in your own simulator
  • Simple, no-cost evaluation license
Start S21 Free Trail

FPGA Bitstream

  • Fully-functional SiFive RISC-V Core Complex with system peripherals
  • High Performance - 32.5 MHz emulation
  • Upload your own programs using the Freedom E SDK

Compatible with the Arty A7-100T FPGA Development Board: