S5 series

S51

The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications

S51
Key Features
  • Fully compliant with the RISC-V ISA specification
  • RV64IMAC Support
    • RV64I – 64-bit RISC-V with 32 integer registers
    • Integer Multiplication and Division (M) support
    • Atomic Mode (A) support for high-performance, portable software
    • Compressed Mode (C) support for better code density
  • Machine and User Mode Support
  • In-order, 5-6 stage variable pipeline
  • Advanced Memory Subsystem
    • 16KB, 2-way Instruction Cache
    • Instruction Tightly Integrated Memory (ITIM) option
    • Up to 64KB Data Tightly Integrated Memory (DTIM) support
  • Support for up to 40 physical address bits
  • Efficient and Flexible Interrupts
    • Local interrupts w/ vectored addresses — up to 16
    • Platform Level Interrupt Controller (PLIC) — 511 interrupts w/ 7 priority levels
    • RISC-V Core Local Interruptor (CLINT) — 1 timer, 1 SW
  • 8-Region Physical Memory Protection (PMP)
  • High performance AMBA Interfaces
  • 2.87/1.74 DMIPS/MHz (Best Effort/Legal)
  • 3.16 CoreMark/MHz
  • Detailed Power, Performance, and Area (PPA) Information
S5 Series
Cortex-R5
Architecture
64-bit
32-bit
Cores
Up to 8 Cores
(fully-coherent)
Up to 2 Cores
(non-coherent)
Interrupt Controller
Included; pre-integrated
Licensed separately; requires integration
L2 Cache Controller
Included (optional); pre-integrated
Licensed separately; requires integration

S51
Development Kit

Dev Kit Deliverables

  • RTL Evaluation
  • Test Bench RTL
  • Software Development Kit
  • FPGA Bitstream
  • Documentation
S5
Series Overview

S5 Series

The S5 Series offers 64‑bit RISC‑V performance with 32‑bit power and area. The S5 core has a 5-6 stage pipeline, offering a great balance between performance and efficiency.

S5 Series
Highlights

Key Features

  • Up to 8 coherent S5 Cores and optional L2 Cache Controller
  • Configurable core performance
  • Double precision Floating Point Unit
  • Level 1 Memory System and ECC
  • Physical addressing up to 47-bits
  • Number, type, and width of bus interfaces
  • Support for SiFive Insight Advanced Trace and Debug

Applications

  • Consumer Electronics
  • Motor Control
  • Industrial Automation
  • Storage
  • High-performance embedded

SiFive Essential
Standard Cores

Area
Standard Cores
ARM Comparison
E2 Series
M0, M0+, M3, M4, M23, M33
E3 Series
R4, R5
E6 Series
M0, M0+, M3, M4, M23, M33
E7 Series
M7, R7, R8
S2 Series
***
S5 Series
R4, R5
S6 Series
***
S7 Series
M7, R7, R8
U5 Series
A5, A7, A35, A53
U6 Series
***
U7 Series
A55
Core Evaluation

From idea
to reality.

Ready to see your code in action? The S51 Development Kit enables free evaluation of SiFive RISC-V Core IP.

Key
Deliverables

Evaluation RTL

  • Full-Functional, synthesizable Verilog RTL
  • Run it in your own simulator
  • Simple, no-cost evaluation license
Start S51 Free Trial

FPGA Bitstream

  • Fully-functional SiFive RISC-V Core Complex with system peripherals
  • High Performance - 32.5 MHz emulation
  • Upload your own programs using the Freedom E SDK

Compatible with the Arty A7-100T FPGA and Xilinx VCU118 Development Boards: