U5 series


The SiFive U54 Standard Core is a single-core instantiation of the world’s first RISC-V application processor, capable of supporting full-featured operating systems such as Linux.

The U54 is ideal for low-cost Linux applications such as IoT nodes and gateways, point-of-sale, and networking.

Key Features
  • Fully compliant with the RISC-V ISA specification
  • RV64GC U54 Application Core
    • 16KB L1 I-cache with ECC
    • 16KB L1 D-cache with ECC
    • 8 Region Physical Memory Protection
    • 48 Local Interrupts per core
    • Sv39 Virtual Memory support with 38 Physical Address bits
  • Integrated 128KB L2 Cache with ECC
  • Real-time capabilities
    • Both the L1 Instruction Cache and the L2 Cache can be configured into high speed deterministic SRAMs
  • CLINT for multi-core timer and software interrupts
  • PLIC with support for up to 128 interrupts with 7 priority levels
  • Debug with instruction trace
  • U54 Performance

    • 2.87/1.7 DMIPS/MHz (Best Effort/Legal)
    • 3.01 CoreMark/MHz

Power, Performance, and Area

28nm HPC
480 MHz
814 MHz
Core-Only Areab
0.147 mm²
0.213 mm²
Core-Only Dynamic Powerc
23.39 μW/MHz
Core-Complex Aread
0.367 mm²
0.394 mm²
Core-Complex Total Powere
25.7 mW

Note: Area and power numbers do not include RAMs and are Post-Route

a. Example Implementations; Area Optimized and Balanced. Frequency is reported at Worst 0.81v, -40°C

b. Core-Only includes the core pipeline, and L1 memory interfaces

c. Power is reported at Typical 0.9v, 25°C for Dhrystone

d. Core Complex includes the Core plus PLIC w/127 irq and 7 priority levels, CLINT, Debug w/2 hw breakpoints, 8 Region PMP, cache Logic, internal bus and AXI ports

e. Core-Complex Total power includes dynamic and leakage and is reported at Typical 0.9v, 25°C

U5 Series
Instruction Set Architecture
M + S + U Mode
ARMv8-A, AArch32, AArch64
Compressed Instruction Support
16-bit instructions
AArch32 only
Physical Memory Protection
MMU only
Real-time capable
Not applicable
Interrupt Controller
Licensed separately; requires integration
Up to 8 cores (heterogeneous)
Up to 4 cores (only Cortex-A53)

Development Kit

Dev Kit Deliverables

  • RTL Evaluation
  • Test Bench RTL
  • Software Development Kit
  • Documentation
Series Overview

U5 Series

The U5 Series features a RISC‑V Linux-capable application processor that offers high performance with maximum efficiency. The U5 core has a 5-6 stage pipeline and supports virtual memory, enabling 64-bit RISC-V applications.

U5 Series

Key Features

  • Up to 9 cores and optional L2 Cache Controller
  • Heterogeneous multi-core with a configurable number of U5 and S5 Cores pre-integrated in a single deliverable
  • U5 and S5 Core performance
  • L1 and L2 memory systems and optional ECC protection
  • Number, type, and width of bus interfaces


  • Low-cost Linux
  • Industrial
  • IoT
  • Storage
  • Networking
  • General-purpose embedded

All Standard

Standard Cores
ARM Comparison
E2 Series
M0, M0+, M3, M4, M23, M33
E3 Series
R4, R5
E7 Series
M7, R7, R8
S2 Series
S5 Series
R4, R5
S7 Series
M7, R7, R8
U5 Series
A5, A7, A35, A53
U7 Series
Core Evaluation

From idea
to reality.

Ready to see your code in action? The U54 Development Kit enables free evaluation of SiFive RISC-V Core IP.


Evaluation RTL

  • Full-Functional, synthesizable Verilog RTL
  • Run it in your own simulator
  • Simple, no-cost evaluation license
Start U54 Free Trial