U5 series
U54
The SiFive U54 Standard Core is a single-core instantiation of the world’s first RISC-V application processor, capable of supporting full-featured operating systems such as Linux.
The U54 is ideal for low-cost Linux applications such as IoT nodes and gateways, point-of-sale, and networking.
U54
Key Features
- Fully compliant with the RISC-V ISA specification
- RV64GC U54 Application Core
- 32KB L1 I-cache with ECC
- 32KB L1 D-cache with ECC
- 8 Region Physical Memory Protection
- 48 Local Interrupts per core
- Sv39 Virtual Memory support with 38 Physical Address bits
- Integrated 128KB L2 Cache with ECC
- Real-time capabilities
- Both the L1 Instruction Cache and the L2 Cache can be configured into high speed deterministic SRAMs
- CLINT for multi-core timer and software interrupts
- PLIC with support for up to 128 interrupts with 7 priority levels
- Debug with instruction trace
- U54 Performance
- 2.87/1.72 DMIPS/MHz (Best Effort/Legal)
- 3.16 CoreMark/MHz
- Detailed Power, Performance, and Area (PPA) Information
U5 Series
Cortex-A53
Instruction Set Architecture
RV64GC
M + S + U Mode
M + S + U Mode
ARMv8-A, AArch32, AArch64
Compressed Instruction Support
16-bit instructions
AArch32 only
Physical Memory Protection
PMP and MMU
MMU only
Responsiveness
Real-time capable
Not applicable
Interrupt Controller
Integrated
Licensed separately; requires integration
Cores
Up to 8 cores (heterogeneous)
Up to 4 cores (only Cortex-A53)
U54
Development Kit
Dev Kit Deliverables
- RTL Evaluation
- Test Bench RTL
- Software Development Kit
- FPGA Bitstream
- Documentation
U5
Series Overview
U5 Series
The U5 Series features a RISC‑V Linux-capable application processor that offers high performance with maximum efficiency. The U5 core has a 5-6 stage pipeline and supports virtual memory, enabling 64-bit RISC-V applications.
U5 Series
Highlights
Key Features
- Up to 9 cores and optional L2 Cache Controller
- Heterogeneous multi-core with a configurable number of U5 and S5 Cores pre-integrated in a single deliverable
- U5 and S5 Core performance
- L1 and L2 memory systems and optional ECC protection
- Number, type, and width of bus interfaces
- Support for SiFive Insight Advanced Trace and Debug
Applications
- Low-cost Linux
- Industrial
- IoT
- Storage
- Networking
- General-purpose embedded
Core Evaluation
From idea
to reality.
Ready to see your code in action? The U54 Development Kit enables free evaluation of SiFive RISC-V Core IP.
Key
Deliverables
Evaluation RTL
- Full-Functional, synthesizable Verilog RTL
- Run it in your own simulator
- Simple, no-cost evaluation license
Start U54 Free Trial
FPGA Bitstream
- Fully-functional SiFive RISC-V Core Complex with system peripherals
- High Performance - 32.5 MHz emulation
- Upload your own programs using the Freedom E SDK
Compatible with the Xilinx VCU118 FPGA Development Board:
