U5 series


The SiFive U54-MC Standard Core is the world’s first RISC-V application processor, capable of supporting full-featured operating systems such as Linux.

The U54-MC has 4x 64-bit U5 cores and 1x 64-bit S5 core—providing high performance with maximum efficiency. This core is an ideal choice for low-cost Linux applications such as IoT nodes and gateways, storage, and networking.

Key Features
  • Fully compliant with the RISC-V ISA specification
  • 4x RV64GC U54 Application Cores
    • 32KB L1 I-cache with ECC
    • 32KB L1 D-cache with ECC
    • 8 Region Physical Memory Protection
    • 48 Local Interrupts per core
    • Sv39 Virtual Memory support with 38 Physical Address bits
  • 1x RV64IMAC S51 Monitor Core
    • 16KB L1 I-Cache with ECC
    • 8KB DTIM with ECC
    • 8 Region Physical Memory Protection
    • 48 Local Interrupts
  • Fully Coherent TileLink Bus
  • Integrated 2MB L2 Cache with ECC
  • Real-time capabilities
    • Both the L1 Instruction Cache and the L2 Cache can be configured into high speed deterministic SRAMs
  • CLINT for multi-core timer and software interrupts
  • PLIC with support for up to 511 interrupts with 7 priority levels
  • Debug with instruction trace
  • U54 Performance
    • 1.7 DMIPS/MHz
    • 2.75 CoreMark/MHz

Power, Performance,
and Area

28nm HPC
Core Only Areaa
Core Complex Areab
Typical: 1.5GHz
Worst: 960MHz

a. Single U54 Core-only data, excludes SRAM; 85% utilization

b. Core Complex data includes single U54 core, 32KB I-Cache, 32KB D-Cache, PLIC, Debug

c. 12 track standard cells. Typical: TT Corner @ 0.9V, 25C, Worst: Slow/Slow, 0.81V, -40C

Compare to
Cortex A-53

Arm Cortex-A53
Instruction Set Architecture
M + S + U Mode
ARMv8-A, AArch32, AArch64
16-bit Instruction Support
Yes RV64C Instructions
Only in 32-bit AArch32 T32 Mode
Physical Memory Protection
Physical Memory Protection (PMP) and MMU
None, MMU only
Real-Time Capabilities
Fast deterministic memory (ITIM, L2-LIM)
Local Interrupts
Physical Memory Protection
Monitor Core
S51 Monitor Core
Licensed separately; requires integration
Interrupt Controller
Licensed separately; requires integration

Series Overview

U5 Series

The U5 Series features a RISC‑V Linux-capable application processor that offers high performance with maximum efficiency. The U5 core has a 5-6 stage pipeline and supports virtual memory, enabling 64-bit RISC-V applications.

U5 Series

Key Features

  • Up to 9 cores and optional L2 Cache Controller
  • Heterogeneous multi-core with a configurable number of U5 and S5 Cores pre-integrated in a single deliverable
  • U5 and S5 Core performance
  • L1 and L2 memory systems and optional ECC protection
  • Number, type, and width of bus interfaces


  • Low-cost Linux
  • Industrial
  • IoT
  • Storage
  • Networking
  • General-purpose embedded

All Standard

Standard Cores
ARM Comparison
E2 Series
M0, M0+, M3, M4, M23, M33
E3 Series
R4, R5
E7 Series
M7, R7, R8
S2 Series
S5 Series
R4, R5
S7 Series
M7, R7, R8
U5 Series
A5, A7, A35, A53
U7 Series