Partner with us to create custom SoC / ASIC / SiP solutions
When standard ASSP products don’t meet your business or technical requirements, it’s time to go custom. Specialized custom SoC / ASIC / SiP solutions can be optimized for power, performance and area, giving you greater design flexibility and a competitive edge.
Front End Design, Integration and VerificationDesign expertise around building tiny low power SoC to large scale SoC with in-house design, integration and advanced verification automated tools and methodology
SoC / ASIC Micro-Architecture
Front End Design
Front End Integration
Front End Verification
IP Development and IntegrationSelecting the correct IP can be challenging, involving lengthy procurement time, legal and business negotiations, and significant technical qualifications. Our IP experts work with customers and vendors to tailor IP solutions that differentiate your product, assure IP quality and reusability, and deliver first-time working silicon. Drawing on an extensive portfolio of third party IP, we can optimize for compatibility, cost, features, PPA (Power, Performance and Area), as well as time-to-market.
What We Factor
IP development (internal or via third party)
IP integration (procurement of IP from third party)
Our Featured Partners
Open-Silicon, a SiFive Company is actively partnering with an ever-growing list of leading vendors to provide the IP blocks, needed to bring new designs to market faster and at reduced cost.
Physical DesignWe’re experts in handling complex ASIC designs. Our innovative design methodology combined with our deep design expertise and experience in the selection, qualification and integration of third party IP, consistently delivers reliable silicon. Following the OpenMODEL™ from Open-Silicon, a SFive Company, our methodology is designed to target multiple process technologies at multiple foundries, and opens the design process to the customer allowing valuable customer feedback during the entire process. We believe that this active partnership ensures that programs are executed to a predictable timetable, with the best results.
Our Design Process
Review architectural requirements and design parameters.
Code features, memories and IP related macros; verify basic chip-level logic.
Freeze design and complete all physical implementation tasks.
Complete design layout and implement customer ECOs.
Complete design layout and implement customer ECOs.
Wafer ManufacturingWe partner with world-class foundries to provide complete manufacturing services. We work closely with our customers to identify and select the right process and technology solution for each design, comparing different foundries, design objectives, market applications and target price. Through our continuous improvement efforts, we provide regular feedback to the foundries as part of the yield enhancement program. We also provide our customers with FIT numbers on regular processes to further ensure the quality of their product.
Integrate design enablement building blocks within TSMC's Open Innovation Platform® (OIP) and provide specific services at each link in the IC value chain, including IP development, design backend, wafer manufacturing, assembly, and testing.
Package and AssemblyWe provide a complete solution, from package selection, through design and development and into high-volume manufacturing. We understand the importance of selecting the proper packaging solution to meet the technical and cost constraints of each design. Our packaging capabilities are very broad including emerging 2.5D technology, and our experience is level very deep, which enables us to meet the unique needs of each customer and successfully launch their product.
What is 2.5D technology
2.5D IC is a packaging technology where multiple die are placed face down and side by side on a silicon or organic interposer. The active surface of the die has micro-bumps that connect to pads on the surface of the silicon interposer. Connections from these pads directly connect to TSVs (Through Silicon Vias), which pass through the interposer substrate and connect to the package substrate. The connections from the pads can also be connected through interposer routing to other TSVs that are in-turn connected to pads and micro-bumps of other die on the interposer. 2.5D IC technology helps reduce interconnection length between multiple dies assembled on the interposer, leading to lower power consumption and lower latency as well as an increase in the number of interconnection routes on the interposer, which results in increased bandwidth compared to traditional 2D off-chip interconnections.
2.5D Technology Diagram
The picture above shows mounting 2 or more silicon dies onto an interposer die and then assembling the whole system into a single package.
Silicon based on 2.5D technology is making inroads into high performance computing, graphic processors, and AI (Artificial Intelligence) processors utilizing High Bandwidth Memories (HBM). These HBMs are available as tested KGDs (Known Good Die), and are mounted on the interposer along with die containing the main processor and HBM controller. High density routing through the interposer interconnects the two die.
The main advantages of this technology are miniaturization, enhanced performance, lower latency, increased bandwidth and power efficiency. Key advantage of 2.5D technology is that the die that are mounted on interposer need not utilize the same process node or technology. This helps in using die manufactured in various technology nodes. As an example, a HBM 3D stacked memory die can be mounted on the interposer with a processor die manufactured in 7nm process technology.
Test, Quality and Supply Chain ManagementIt is through continual improvement in our processes that we will achieve the goal of increasing customer satisfaction while making it easier for our customers.
ISO 9001:2015 Certificate
Open-Silicon, a SiFive Company has established the standard to demonstrate the ability to consistently provide products and services that meet customer and regulatory requirements, earning the ISO 9001:2015 Certificate.
We view test engineering as an essential part of the design process, so we address test very early in the design cycle. Our test engineers have extensive design for testability (DFT) experience with a variety of automatic test equipment (ATE). This allows us to create a smooth transition from a simulation environment to a tester environment, thus avoiding getting stuck in endless loops while debugging test vectors.
Supply Chain Management
Our experienced Production Control (PC) team plays a crucial role once the customer releases their part to production. This team performs and monitors the following activities to guarantee on-time delivery:
• Scheduling, planning and forecasting
• Wafer, assembly and test management
• Inventory management
• 24×7 automated WIP tracking and reporting via ASICView
• Shipments tracking