Manager/Principal Engineer - Physical Design
At Open-Silicon, a SiFive company, we design, develop and deliver advanced semiconductor solutions for a range of verticals and industries. We invented RISC-V, and our extensive line-up of best-in-class RISC-V processor cores has over 150 adoptees worldwide, including tier-1 semiconductor companies. Our custom SoC division delivers ASICs in the most advanced technology nodes and enjoys close partnerships with all leading silicon foundries. We push the envelope on advanced ASICs for artificial intelligence and machine learning. Our ASICs are also seen in satellite communication systems, IoT and extreme low-power mobile devices. We are leaders in high-speed networking and memory interface IP. With our expertise in package-silicon codesign, we belong to the technology elite that can deliver leading-edge products based on 2.5D interposer technology and 3D packaging. We have a global presence with multiple development centers in North America, Europe, China, Korea and India. Our design centers in India, located in Bangalore and Pune with additional sites under development, drive innovation and deliver solutions across our product portfolio. To support our growth and expansion plans, we are hiring across disciplines, including SoC architecture, analog design, logic design and verification, DFT, physical design, embedded software and board and system design.
(10-15 years Experience)
- Should be able to technically lead a team and execute all aspects of RTL to GDS implementation for a Complex ASIC.
- Should be hand on and thorough in complex hierarchical chip Implementation.
- Should be able to breaks down the tasks, assign and track the progress.
- Should demonstrate problem solving, debug and mentorship skills.
- Should be able to work with cross functional teams and resolve cross functional dependencies.
- Should have strong communication skills. Should have experience in working with customers and vendors and should be able to articulate technical problems and find resolution.
- Experience is IP hardening like DDR/HBM/Serdes PHY
- Experience in 2.5D ASIC Design, Interposer design, Spice simulations, customer circuit design, SI/PI, Packaging & chiplet design is a big plus