SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.
Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of workload-focused hardware needed to design next-generation products.
- Evolve, design and build new compiler intermediate representations for hardware design and tool flows.
- Implement specific compiler optimization and lowering algorithms for chip design flows.
- Implement state of the art mechanisms for hierarchical caching that crosscut compiler and build systems.
- Participate in design discussions, planning, code review, documentation, open source processes, and other standard software practices.
- Collaborate with hardware architects to develop the approach and design flows.
- Manage your individual project priorities, deadlines and deliverables.
- We are hiring for several positions with different levels of seniority, but require a minimum of 2 years of compiler engineering experience.
- Strong oral and written communication skills, excellent team collaboration.
- Experience with C++ programming and git-based development workflows.
- Experience with Verilog and other chip design technologies is NOT required.