SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.
Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of workload-focused hardware needed to design next-generation products.
As the Power Architect at SiFive, you are vital to our efforts to create silicon at the speed of software. You will be involved with the design and definition of various aspects of SiFive’s power architecture — both within the core and at the SoC (System-on-a-Chip) level. Such designs will include architecture specification for clock and power gating, DVFS, and core & SoC power states. You would also have the opportunity to craft power models to drive multiple power-optimized processor and SoC designs.
You will create new, highly configurable power-optimized designs, based on the open-source RISC-V ISA, for SiFive’s clients, who are taking on exciting new use cases—like autonomous driving, 5G networking, wearables, or IoT. At SiFive, you will find the unique chance to design power architecture more quickly and for far more devices than would be technologically possible at any other company, because we are reducing the time needed for IP and chip design and verification down from months to weeks.
- Designing and defining the specifications of various elements of core and SoC-level power architecture. Examples include clock gating, power dating, DVFS, core and SoC power states, execution throttling, etc.
- Developing the upcoming power-optimized multicore platform, which will connect numerous cores together on a chip, support large bandwidth, as well as new applications and workloads.
- Researching and analyzing emerging needs for new power-optimized core architectures.
- Working closely with our customers to tailor power-optimized cores to their needs.
- 8+ years of experience in power architecture definition.
- Familiarity with advanced CPU pipelines and SoC architectures, as well as advanced power design concepts, such as DVFS, and thermal management techniques.
- Proven experience in core or SoC design flow, including spec definition, microarchitecture design, and power modeling.
- Basic understanding of: RTL design & SoC tool flows, including UPF; foundry lib, IP, and process technology limitation; memory management.
- Excellent teamwork and interpersonal skills.