RTL Design Engineer - RISC-V CPU
SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.
Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of workload-focused hardware needed to design next-generation products.
- Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators.
- Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
- Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
- Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
- Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
- BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
- Academic or Professional experience with CPU RTL design.
- Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
- Knowledge of at least one object-oriented and/or functional programming language.
- Experience with designing an out-of-order system ( high-performance DDR controller or caches controllers on a hetro/homo-geneous multi core system is a plus.
- Expertise in CPU processor designs in one or more of the following areas is a plus: instruction fetch and decode; branch prediction; register renaming and instruction scheduling; integer; floating-point, and vector units; load-store unit; cache and memory subsystems.
- Knowledge of verification principles, testbenches, UVM, and coverage is a plus.
- Knowledge of RISC-V architecture is a plus.
- Experience with Scala and/or Chisel is a plus.
- Attention to detail and a focus on high-quality design.
- Ability to work well with others and share the belief that engineering is teamwork.
SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off, health benefits, an employee stock option program, and much more.
In addition to these, in the Taiwan office, we provide regional benefits including team-building events, annual health examination, and education reimbursement.
We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.
If you yearn to be challenged and wish to work in an environment where the boundaries of your creativity and skills will be tested, then SiFive is the place for you.