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Qemu System Modeling Engineer
SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.
Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of workload-focused hardware needed to design next-generation products.
As a QEMU Engineer in the System Software Team, you will work with system architecture and hardware engineering teams to help design and evaluate systems, including CPUs, interconnects, firewalls, and related IP blocks. You’ll work with our software group to design software implementations that take advantage of hardware features and integrate cleanly with existing operating systems, such as Linux. You’ll write software for QEMU to model IP and instruction set. You’ll be a part of creating something big, all based around the RISC-V instruction set architecture.
- Design, develop and upstream QEMU and other simulation solutions (both SiFive-proprietary and public open source)
- Engage with architecture, hardware engineering, and other software engineering teams to review, and refine features
- At least 3 years’ experience developing QEMU for both instruction set and peripheral IP modeling, with upstream involvement
- Strong communication, co-working, and listening skills
- Experience working with hardware architecture and engineering teams
- Experience debugging complex multicore systems
- Experience debugging with GDB
- Experience with git, Makefile, GNU toolchain and shell scripting
- Deep understanding of computer architecture at the CPU and system levels
- Understanding of VLSI design concepts and how they impact hardware and software architecture
- Ability to read HDLs such as Verilog/Chisel