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Senior Physical Design Engineer
SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.
Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of workload-focused hardware needed to design next-generation products.
As a Physical Design Engineer in the Implementation team, you will contribute to the development of industry-leading CPU IP to support the SiFive vision of enabling chip design by anyone. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
The person in this role can work out of our offices in the Bay Area, CA or Austin, TX. However, due to the current restrictions surrounding COVID-19, this position is work-from-home until further notice.
- Implementing and optimizing our broad portfolio of RISC-V CPU's from RTL to GDSII.
- Closing bold performance, power, and area (PPA) goals at block and/or CPU level.
- Collaborating with the microarchitecture and RTL teams to optimize PPA trade offs.
- Contributing to physical implementation flow development to drive best in class automation and PPA.
- 10+ years of physical implementation experience (including experience with CPU designs) with multiple tape outs in a wide range of technologies (16nm and below); Experience with advanced process nodes (7nm and below) is strongly preferred.
- Expertise in synthesis, DFT insertion, floorplanning, place and route, clock tree synthesis, static timing, power analysis, and signal and power integrity.
- Experience with physical signoff (DRC/ANT/LVS/DFM, etc.) and engineering change orders (ECO's).
- Knowledge and skill in optimizing PPA through floorplanning, placement and timing constraints, useful skew, and similar techniques.
- TCL and Python scripting.
- Attention to detail and a focus on high-quality design.
- Ability to work well with others and a belief that engineering is a team sport.