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Senior RTL Design Engineer
SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.
Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of workload-focused hardware needed to design next-generation products.
As a RISC-V RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
- Architecting, designing and implementing new features, performance improvements, and ISA extensions in RISC-V CPU cores and TileLink interconnect, protocol bridges, and other infrastructure/uncore logic.
- Microarchitecture development and specification. Ensuring that knowledge is shared via great documentation and participation in a culture of collaborative design.
- Performing initial sandbox verification, and working with the design verification team to create and execute thorough verification test plans.
- Working with the physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
- Collaborating with the performance modelling team for performance exploration and optimization to meet performance goals.
- 8+ yrs of recent industry experience in high-performance, energy-efficient CPU/SoC designs.
- Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
- Experience with Scala and/or Chisel is a plus.
- Knowledge of RISC-V architecture is a plus.
- Experience with NoC or other interconnect fabrics.
- Attention to detail and a focus on high-quality design.
- Ability to work well with others and a belief that engineering is a team sport.
- Knowledge of at least one object-oriented and/or functional programming language.
- Background of successful CPU development from architecture through tapeout.
- MS/ PhD degree in EE, CE, CS or a related technical discipline, or equivalent experience.