San Mateo, CA
Verification
Full-Time

Memory Subsystem Verification Engineer

About SiFive
SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP & SoC IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.
Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our shown success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of domain-specific hardware needed to design next-generation products.
SiFive was founded and is actively run by the developers of RISC-V. If you are passionate about working with industry leaders and innovators, then send us your application today!
As an experienced Verification Engineer on the Design Verification team, you will participate in the definition, implementation, and execution of our verification strategy, as well as being a key participant in the analysis of our verification quality of results. This verification position is a highly visible role, the simple purpose of which is to ensure the silicon works.
What will you work on when you join our team? By its design philosophy, RISC-V is highly configurable, and we have several different configurations in our design pipeline, with various combinations of supported instruction set and with various peripherals and bus interconnect architectures. This role is for the verification of our CPU memory sub-system including caches, virtual memory, and system connections that use AMBA and TileLink protocols. 
LOCATION: The person in this role can work out of our offices in the Bay Area, CA or Austin, TX. However, due to the current restrictions surrounding COVID-19, this position is work-from-home until further notice.

Responsibilities

  • Architect test methodologies applicable to a wide range of CPU and SoC designs for CPU memory sub-systems including Load-Store unit, various levels of caches, memory virtualization and industry standard bus protocols (e.g. AMBA and TileLink).
  • Understand CPU caches and SoC designs from an architectural level and create effective verification strategies for these designs.
  • Build test plans to implement these strategies, considering issues such as design feature priority, potential customer impact, coverage metrics generation and measurability, etc.
  • Develop tools, test benches, and test suites (UVM, C++/C or otherwise, as needed) to execute test plans.
  • Provide technical leadership for verification engineers and coordinate technical teams to execute our verification strategies to meet program goals.
  • Collaborate closely with the design team on feature specifications, test plans and failure analysis.

Requirements

  • 7+ years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, System Verilog, Verilog, Makefiles, scripting languages, etc.), especially in hands-on testbench development and test suite generation.
  • Solid understanding of CPU and SoC memory architecture including Load-Store unit, various levels of caches, cache coherence protocols, virtual memory, bus interface units, and memory controllers. 
  • Experience with industry standard system bus protocols (e.g. AMBA AXI, AHB, APB) is preferred. Knowledge of TileLink is a plus.
  • A thorough understanding of the high-level verification flow methodology (testplan generation, test generation, failure analysis, coverage analysis and closure).
  • Ability to effectively assess the design verification metrics, remaining state space to be covered, and efficient methods to achieve verification closure.
  • Verification experience in test planning, constrained random test generation, test stimulus, code coverage, functional coverage.
  • Ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.).
SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off; health, vision, and dental benefits; 401(k) plan; employee stock option program, and much more.
We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.
If you yearn to be challenged and wish to work in an environment where the boundaries of your creativity and skills will be tested, then SiFive is the place for you. 
Notice to Staffing Agencies / External Recruiters:
Thank you for your interest in SiFive Inc. Please note that SiFive does not accept unsolicited resumes from external agencies unless contracted to fill a specific position. Agencies are hereby specifically directed NOT to contact SiFive employees directly in an attempt to present candidates – all applications must go through SiFive's internal recruiting team. Any third-party resume forwarded by agencies/external recruiters to a SiFive mailing address, fax machine or email address, directly to SiFive employees, or to SiFive's resume database will be considered property of SiFive Inc and treated as a direct application. This exchange does not constitute an agreement between SiFive and the agency/external recruiter. SiFive reserves the right to contact the candidate directly. Employment agencies/external recruiters will receive no compensation from SiFive or its companies.