Design for Test (DFT) Engineer

As a DFT Engineer in the Implementation Team, you will develop DFT specifications, plan and implement DFT tool flows to meet industry standard test requirements for HVM including Memory BIST, Logic BIST, boundary scan, and at speed scan test with compression.


  • Implement, integrate and verify DFT logic designs at IP level and chip level
  • Provide signoff timing constraints for all DFT modes and collaborate with physical design team to close timing and physical design signoff requirements
  • Generate production quality manufacturing test patterns and assist with bring-up and debug on ATE.

Minimum qualifications

  • Extensive experience of ASIC design for test including complete silicon life cycle through DFT pattern bring-up on ATE and manufacturing
  • Experience in one or more of the following physical design flows and methodologies: synthesis, static timing analysis (STA), formal verification and power intent (UPF/CPF).
  • Good scripting skills using Tcl, Perl, Python, Makefile and Shell scripts

Preferred qualifications

  • Experience working with FinFET process nodes
  • Experience and/or knowledge in hierarchical DFT and physical design flows, and IP integration (SRAM, IO, hardened digital IP and analog IP).
  • Experience with ATPG tools/and or production testing