San Mateo, CA

Interconnect/UnCore Design Engineer

RISC-V is a groundbreaking CPU instruction set architecture. Along with being an open-source instruction set, RISC-V is informed by decades of industry experience with various RISC processor designs, while being unencumbered with the necessity of backward compatibility. It is a unique opportunity to base a processor design on sound engineering principles, and the successful applicant will have comprehensive daily hands-on exposure to this architecture. While several companies are pursuing RISC-V design, only SiFive is founded and actively run by the inventors of RISC-V. This is not an academic exercise; we have real customers and real silicon.
SiFive is looking for hardware engineers who are passionate about designing industry-leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creating massively customizable IP and improving time-to-market by designing hardware as highly-configurable generators. We're using technology and ideas from the software industry to execute hardware design with the agility of software development.
We build and maintain multiple CPU lines, TileLink interconnects and other uncore/infrastructure IP using the Chisel hardware construction library embedded in the Scala language, and are seeking motivated individuals to improve/evolve our existing IP as well as develop new IP.
Join us, and surf the RISC-V wave with SiFive!


  • Architect, design and implement and enhanced TileLink interconnect, high-level cache controllers, protocol bridges, and other infrastructure/uncore logic as RTL generators in Chisel; including both open-source and proprietary designs;
  • Implement RTL generators such that elements self-configure to optimally connect to each other;
  • Improve future designs to provide higher performance, more efficient multi-core and multi-system coherence;
  • Design extensive configurability in as a first-class consideration;
  • Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software;
  • Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans;
  • Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design.


  • Knowledge of cache and cache coherency architectures and concepts;
  • Experience with NoC or other interconnect fabrics;
  • Familiarity with industry-standard bus protocols (AMBA et al);
  • Ability to architect solutions to connect bus fabrics of disparate protocols;
  • Strong software engineering skills/background, including:
  • Object-oriented, aspect-oriented, and particularly functional programming
  • Templated metaprogramming, in any language
  • Compiler infrastructures, particularly for domain-specific languages;
  • Data modeling, particularly intermediate representations for optimizing or transforming compiler passes;
  • Test-driven development, particularly ability to write adaptive unit tests;
  • Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL;
  • Attention to detail and a focus on high-quality design;
  • Ability to work well with others and a belief that engineering is a team sport;
  • BS/MS in EE, CE, CS or a related technical discipline, or equivalent experience.
SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off, health, vision and dental benefits, 401(k) plan, employee stock option program, and much more. If you yearn to be challenged and wish to work in an environment where the boundaries of your creativity and skills will be tested, then SiFive is the place for you.