San Mateo, CA
RISC-V
Full-Time

Formal Verification Engineer

As an experienced formal verification engineer, you join our team as a senior engineer who will envision, enable and execute on world class verification and validation of RISC-V microprocessor cores, sub-systems, IPs and SoCs. Starting from the SiFive roadmap and pipeline of products, you will get to make proactive plans to ensure we verify our products to high levels of quality. You will be a key player in executing these plans.
What will you work on when you join our team? By its design philosophy, RISC-V is highly configurable, and we have several different configurations in our design pipeline, with various combinations of supported instruction set and with various peripherals and bus interconnect architectures. Implementing design verification methodologies that can accommodate such variation is a challenging task, to be addressed in this role.

Qualifications

  • Strong background in formal reasoning
  • Experience using industry standard formal verification tools such as Jasper

How can you improve your candidacy?

  • Object-oriented, functional programming experience
  • Background in Computer Architecture