Senior Engineer - DFT

At Open-Silicon, a SiFive company, we design, develop and deliver advanced semiconductor solutions for a range of verticals and industries. We invented RISC-V, and our extensive line-up of best-in-class RISC-V processor cores has over 150 adoptees worldwide, including tier-1 semiconductor companies.  Our custom SoC division delivers ASICs in the most advanced technology nodes and enjoys close partnerships with all leading silicon foundries. We push the envelope on advanced ASICs for artificial intelligence and machine learning. Our ASICs are also seen in satellite communication systems, IoT and extreme low-power mobile devices.  We are leaders in high-speed networking and memory interface IP. With our expertise in package-silicon codesign, we belong to the technology elite that can deliver leading-edge products based on 2.5D interposer technology and 3D packaging. We have a global presence with multiple development centers in North America, Europe, China, Korea and India. Our design centers in India, located in Bangalore and Pune with additional sites under development, drive innovation and deliver solutions across our product portfolio. To support our growth and expansion plans, we are hiring across disciplines, including SoC architecture, analog design, logic design and verification, DFT, physical design, embedded software and board and system design.
Senior DFT Engineer
If you are a top-notch DFT engineer who would thrive in a fast-paced environment where you are empowered to innovate, encouraged to learn, and expected to lead, get in touch.
Job Description:
You should have an intimate understanding of DFT concepts and methodologies for scan/ATPG, memory BIST and JTAG/boundary scan. Familiarity with Vtran or Simutest will be great. You should be able to independently handle complete DFT insertion at full chip level and understand IP test requirements.  You should have a demonstrated ability in Verilog coding and test bench development, and be fully conversant with test-mode timing, static timing analysis and SDC. You will handle post-silicon pattern generation, validation and ATE debug/support. You will create DFT specifications. You should be an expert in the use of relevant industry-standard EDA tools. Good scripting skills in Tcl and Perl is a big plus. You will independently debug any issues in implementation and verification, and be able to help other team members.