San Mateo, CA
Senior Verification Engineer
RISC-V is a groundbreaking CPU instruction set and architecture. Along with being an open-source instruction set, RISC-V is informed by decades of industry experience with various RISC processor designs, while being unencumbered with the necessity of backward compatibility. It is a unique opportunity to base a processor design on sound engineering principles, and the successful applicant will have comprehensive daily hands-on exposure to this architecture. While several companies are pursuing RISC-V design, only SiFive is founded and actively managed by the inventors of RISC-V. This is not an academic exercise; we have real customers and real silicon.
As a Senior Verification Engineer on the Design Verification team, you will participate in the definition, implementation, and execution of our verification strategy, as well as being a key participant in the analysis of our verification quality of results.
This verification position is a highly visible role, the simple purpose of which is to ensure the silicon works. What will you work on when you join our team? By its design philosophy, RISC-V is highly configurable, and we have several different configurations in our design pipeline, with various combinations of supported instruction set and with various peripherals and bus interconnect architectures. Implementing design verification methodologies that can accommodate such variation is a challenging task, to be addressed in this role.
- Architect test methodologies applicable to a wide range of processor and SoC designs
- Perform initial debug of test failures to identify design errors
- Collaborate closely with the design team to address any design errors
- Understand custom microprocessor and SoC designs from an architectural level, and use this understanding to envision effective verification strategies for these designs
- Create a test plan to codify this strategy, taking account of such issues as design feature priority, potential customer impact, coverage metrics generation and measurability, etc.
- Create test suites (UVM, C, or otherwise, as needed) to execute this strategy
- Drive the execution of these test suites (scripting, Makefiles, etc.)
- Analysis of test results, including RTL or higher-level debug of test failures
- Interact with the design team to help drive bug closure
What you bring to the challenge
- A minimum of 3 years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, Verilog, Makefiles, scripting languages, etc.) - especially in hands-on testbench and test suite generation
- A conscientious and thorough approach to Design Verification - Attention to detail. Thoroughness is essential in this role.
- Solid understanding of processor and SoC architecture, or a strong desire and ability to learn same
- A thorough understanding of the high-level verification flow methodology (testplan generation, test generation, failure analysis, code coverage, iteration until coverage closure).
- Ability to effectively assess the current state of a design’s verification posture, remaining state space to be covered, and efficient methods to achieve verification closure
- Ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.)
- Master’s degree required with emphasis in Electrical Engineering, Computer architecture, or Computer Science