San Mateo, Portland, Austin
Physical Implementation Engineer
As a Physical Design Engineer in the Implementation Team, you will participate in the tape out of chips to support the SiFive vision of enabling chip design by anyone. When you join our implementation team as a physical design engineer, you will take ownership and contribute as an implementation expert with comprehensive RTL to GDS experience who has taped out multiple ASICs with a wide range of process and technologies (180nm ~ 28nm). 16nm and below is a bonus.
- You will work on chips from RTL to GDSII that push the cutting edge of automation;
- You will get to solve issues outside of the typical physical design flow;
- You will join a team working to revolutionize the chip design industry: Instead of the question being, “how many engineers it takes to do a chip?” we want to reframe it to ask, “how many chips an engineer can make?”;
- Join us as we create a fully automated online chip design methodology.
What you bring to the challenge
- Synthesis and DFT insertion;
- Static Timing Analysis and Timing Closure;
- Low-power design experience (power distribution, analysis, optimization, EM/IR);
- Floorplanning and physical hierarchy partitioning and budgeting;
- Understanding of DFT and its ramification to implementations;
- Clock tree synthesis and optimization;
- Detailed routing and signal integrity;
- Engineering change order (ECO): logic ECO, metal-only ECO, spare-gates and gate-arrays;
- Physical signoff (DRC/ANT/LVS/DFM, etc.).
- Bachelor’s degree in Electrical Engineering or Computer Engineering, Master’s preferred
SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off, health, vision and dental benefits, 401(k) plan, employee stock option program, and much more. If you yearn to be challenged and wish to work in an environment where the boundaries of your creativity and skills will be tested, then SiFive is place for you.