September 23, 2019
SiFive Announces Key Enablement Of Trace And Debug
World Leading RISC-V IP Portfolio with integrated Instruction Trace Encoder
SAN MATEO, Calif. – September 23rd, 2019 – SiFive, Inc., has announced the general availability of the latest update to SiFive Core IP and SiFive Core Designer in the Q3 2019 quarterly update. This release is specifically focused on the enablement of Trace and Debug functionality in the development of configurable SoC design.
Real-time analysis enabled via tracing permits a deeper insight into the interactions of software and hardware to accelerate development, debug, and validation. To support this goal, the full range of SiFive Core IP is now enabled with Nexus 5001™ Instruction Trace capabilities.
Configuring a SiFive Core IP project with advanced trace capabilities can now be performed in SiFive Core Designer. The core complex design including Nexus 5001™ trace encoders is configured in SiFive’s cloud environment and delivered pre-integrated and verified in a single package to save silicon design teams time, money, and engineering resources.
Open-source contributions are a core value for SiFive, and clearly demonstrated by the immediate availability of a SiFive contributed open-source cross-platform, C++ based, Nexus 5001™ Trace decoder for RISC-V on Github, to ease integration into existing debug and trace environments.
Through the use of Nexus 5001™ trace, SiFive processors are supported by a number of leading industry tools:
“As a leader in the debug space, we are pleased to work with SiFive to expand the trace and debug offerings available for RISC-V,” said Anders Holmberg, Chief Strategy Officer, IAR Systems, “Our mission is to make software development easier, faster, and more robust, and we are confident that the debug and trace features SiFive now adds will contribute to that vision. We will continue to collaborate and share knowledge in order to ensure the RISC-V community have access to the tools needed to take RISC-V development to the next level.”
“As a leading provider in the embedded debug space, Lauterbach are pleased to adopt SiFive Core IP as part of our Trace and Debug support,” said Stephan Lauterbach, Lauterbach CTO, “The Lauterbach mission is to accelerate software development, and the addition of SiFive’s debug and trace features in our product line delivers on that vision. The momentum of SiFive and their excellent industry engagement made deciding to invest in bringing debug and trace support for SiFive RISC-V development, simple.”
“We are excited to be working with SiFive in further advancing debug and trace for RISC-V,” said Rolf Segger of SEGGER Microcontroller. "The decision to put engineering efforts into support for the SiFive Trace IP was an easy one thanks to their adoption of industry standards, their strong business momentum, and the ease of dealing with the SiFive team. We believe this is great news for SiFive, SEGGER, and the RISC-V community.”
“SiFive continues to lead in the RISC-V ecosystem,” said Yunsup Lee, SiFive CTO and co-founder, “as demonstrated by this update that enables SiFive to be first to offer a full portfolio of RISC-V based microarchitectures with integrated instruction trace, supported by major software providers. SiFive based platform development is now simpler and more robust than ever before, leading the industry in ease of adoption.”
SiFive momentum continues to grow with the fast-paced evolution of silicon design enablement, RISC-V IP, and solution support offered by the company. For more details about SiFive Trace and Debug enablement inside the SiFive Q3 quarterly update, visit https://www.sifive.com/blog/making-it-easy-to-do-it-right.
SiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.
Leslie Clavin SHIFT Communications for SiFive 415-591-8440 email@example.com