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December 04, 2018
SiFive Announces Multiple Technical Advances at RISC-V Summit
SiFive leads RISC-V ecosystem at inaugural summit with range of cores, RISC-V silicon, proof points, demonstrations, partnerships, talks and panels
SANTA CLARA, Calif. — Dec. 4, 2018 — SiFive, the leading provider of commercial RISC-V processor IP, today announced a series of technical advancements during the inaugural RISC-V Summit. The leading provider of commercial silicon based on the open source RISC-V instruction set architecture, SiFive, demonstrated the strength of its product offerings via a number of product demos, keynote talks and panel participation.
SiFive recently secured significant double-digit design wins across its Core IP 2, 3, 5, and 7 Series. Of those, more than 10 design wins were for their highly successful E2 Core IP Series, it was revealed at the inaugural RISC-V Summit in Santa Clara. The design wins represent the rapidly growing adoption of SiFive's RISC-V based IP in a wide array of use cases by some of the industry's largest brands. Some customers with complex implementations chose to bundle E2 Core IP with higher performance E3, E5, and E7 Core IP Series. These in-cluster combinations demonstrate the completeness of SiFive's Core IP, particularly in constrained designs where architectural customization and optimization stand to offer substantial real-world performance advantages. SiFive will be announcing further details in the coming weeks.
Krste Asanovic, co-founder and chief architect at SiFive as well as an inventor of the RISC-V ISA and chairman of the RISC-V Foundation, will present the "RISC-V State of the Union" today to kick off the Summit. During the session, Asanovic commented on the progress the ecosystem has made in the past four years.
Other Summit presentations by SiFive include:
Embedded Intelligence Everywhere by Jack Kang, Tuesday, 1:10 p.m. to 1:30 p.m.
NVIDIA's Deep Learning Accelerator meets SiFive's Freedom Platform by Yunsup Lee and Frans Sijstermans, NVIDIA, Tuesday, 1:35 p.m. to 1:55 p.m.
SiFive Freedom Revolution: Customizable RISC-V AI Platform with HBM2 and 56-112Gb/s SerDes by Krste Asanovic, Tuesday, 2 p.m. to 2:20 p.m.
Opportunities and Challenges of Building Silicon in the Cloud by Yunsup Lee, Wednesday, 9 a.m. to 9:20 a.m.
SiFive TERP: A Trusted Execution Reference Platform for Embedded Secure Applications by Palmer Dabbelt and Nathaniel Graff, Wednesday, 2:40 p.m. to 3 p.m.
Expansive Array of Demos
SiFive also will feature a wide array of chips and devices based on its core IP at its Booth, No. 202.
Microsemi will demonstrate an object detection algorithm running on their current expansion board. Announced at the RISC-V Summit, Microchip's new PolarFire SoC FPGA architecture, in collaboration with SiFive, brings real-time deterministic asymmetric multiprocessing capability to Linux platforms in a multi-core, coherent CPU cluster. The PolarFire SoC FPGA architecture includes SiFive's U54-MC and features a flexible 2 MB L2 memory subsystem that can be configured as a cache, scratchpad or a direct access memory. This allows designers to implement deterministic real-time embedded applications simultaneously with a rich operating system for a variety of thermal and space constrained applications in collaborative, networked IoT systems, all in a single, coherent central processing unit (CPU) complex.
Rambus and SiFive will showcase SiFive's FU540 processor integrated with the Rambus CryptoManager Root of Trust (CMRT). The Rambus CMRT soft IP core is delivered as Verilog RTL for inclusion in any chip or FPGA design. Features include a security-optimized multi-stage 32-bit RISC-V RV32I based processor, self-contained secure boot, memory protection unit locked at boot time, private SRAM and CPU bus isolated from secure key bus. The CMRT uses a layered security model for software, using the hardware enforced privilege levels of the RISC-V ISA for separation of data between layers (user, supervisor, machine).
SiFive will display FADU's Annapurna SSD controller featuring SiFive's industry-leading 64-bit, E51 multicore RISC-V Core IP. The FADU Annapurna SSD controller is the world's first RISC-V based SSD controller and provides the highest throughput (3.5GB) and IOPS (800K) among its peers, while consuming less than 1.8W active power. Powered by FADU Annapurna, the FADU Bravo SSD is the first 7mm low-power U.2 supporting dual port and offers 3-4X IOPS / watt greater efficiency, 30 percent lower power and the most consistent latency QoS in its class. Despite consuming only 6W to 8W of active power, FADU Bravo easily outperforms competing solutions at 25W, due to its innovative design, advanced flash memory controller and use of SiFive's high-performance 64-bit embedded RISC-V Core IP.
SiFive also will display a silicon development board by Upbeat. The wearable chip is based on SiFive's E31 Core IP and is optimized for low-power, wearable applications and features a built-in AI inference and graphics accelerator engines.
Eideticom will be demonstrating their NoLoad™ NVM Express Computational Storage Accelerator.
SiFive will demonstrate Debian Linux running on SiFive's HiFive Unleashed board and Microsemi's expansion board (over 94 percent of Debian packages have been ported to RISC-V).
Additionally, SiFive will demonstrate a flexible AI application constructed with a standard Linux-capable design. The YOLO (You Only Look Once) image recognition application was constructed with the open-source NVDLA framework, demonstrating the flexibility of the hardware and software stack. The demo consists of the NVDLA accelerator running on an FPGA connected via ChipLink to SiFive's HiFive Unleashed board powered by the Freedom U540, the world's first Linux-capable RISC-V processor. The complete SiFive implementation is well-suited for intelligence at the edge, where high performance with improved power, performance and area profiles are crucial. SiFive's silicon design capabilities allow a simplified path to building custom silicon on the RISC-V architecture with NVDLA.
Many other demos will use SiFive's development boards, including Western Digital's NAS demonstration of their state-of-the-art SMR (Shingled Magnetic Recording) hard disk connected to a HiFive Unleashed board and Microsemi expansion board.
OnChip will highlight an SoC prototype that integrates a 32-bit E31 RISC-V IMAC based core featuring a low-energy, always on (AON) subsystem with peripherals for low-duty-cycle sensor node applications.
The Keystone research project, currently led by research groups at UC Berkeley, including Asanovic, and CSAIL at MIT will demonstrate an open source secure hardware enclave. This allows the building of trusted execution environments (TEE) with secure hardware enclaves, based on the RISC-V architecture.
Robust Tools Available
The RISC-V technology and ecosystem are evolving rapidly. With the rapid growth, the need for professional development tools is increasing. SiFive is working closely with the leading tool providers to improve RISC-V support by commercial providers of compilers, debuggers, IDEs, trace units and development platforms. Alongside SiFive's own Freedom SDK, a fuller development stack and toolchain is rapidly making its way to market.
IAR Systems and SiFive have collaborated to bring IAR Systems' leading compiler and debugger technology to users of SiFive's high-performance and highly configurable core IP. By tightly integrating IAR's industry-leading compiler and debug tools with SiFive's industry-leading RISC-V Core IP, the companies will provide developers with powerful, easy-to-use, complete solutions enabling users to get started quickly.
IAR, Segger, Lauterbach, Ashling and Green Hills Software tools all support SiFive RISC-V Core IP and will be demonstrated at SiFive's booth.
Partner Ecosystem Momentum
With the recent signing of PLDA's extensive suite of PCIe controllers, SiFive DesignShare program has grown to 17 partners and includes: Analog Bits, ASIC Design Services, Brite Semiconductor, Chipus, Chips & Media, Dover, eMemory, FlexLogix, Mobiveil, OpenEdges, PLDA, Rambus, Terminus Circuits, Think Silicon, UltraSoC and Wasiela. The range of IP on offer via the unique IP sharing program now ranges from analog and mixed signal IP to ultra-low power and security IP, broadly covering IP needs for SoC designers. The IP selection on offer is particularly well integrated for IoT, edge, networking and storage, AI/ML, wearables and intelligent embedded applications.
SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit www.sifive.com.
SHIFT Communications for SiFive