April 08, 2019

SiFive to Present at Leading IP, Processor Conferences

Executives to discuss new business models, optimizing RISC-V based processors and customizing architectures for AI implementations at Design and Reuse IP-SOC day and Linley Group events

WHO: SiFive, the leading provider of commercial RISC-V processor IP, and the following executives:

  • Sunil Shenoy, SVP/GM RISC-V IP BU
  • Yunsup Lee, co-founder and chief technology officer
  • Krste Asanovic, co-founder and chief architect

WHAT: SiFive executives will present at Design and Reuse IP-SOC Day 2019 and the Linley Spring Processor Conference 2019, both in Santa Clara, Calif. As SiFive continues its mission to democratize access to custom silicon, the company will present the following sessions:

  • Tuesday, April 9 at Design and Reuse, IP-SOC Day

    • 12:15 p.m. "IP Democratization: Which Enablers? New Business Model, IP Central or Design Marketplace?"
      • Sunil Shenoy will participate on a panel with executives from Andes Technology Corp., ARM, efabless Corp., Intel and Sankalp Semiconductor to discuss the need for vendors to adopt new business models and democratize access to semiconductor IP to survive in today's global economy.
  • Wednesday, April 10 at the Linley Spring Processor Conference

    • 10:20 a.m. – "Extending and Optimizing 64-Bit RISC-V Processors"
      • Yunsup Lee will discuss the changing nature of modern compute loads, and the impact of intelligence moving from the enterprise core to the edge. This presentation will highlight recent advancements in extending and optimizing SiFive's 64-bit RISC-V processors to enable heterogeneous compute and efficiency.
  • Thursday, April 11 at the Linley Spring Processor Conference

    • 1:15 p.m. – "Freedom Revolution: Customizable RISC-V AI SoC Platform"
      • Krste Asanovic will outline a new domain-specific architecture approach for AI SoCs, centered on high-performance machine-learning processors based on customizable RISC-V cores with vector extensions, HBM2 high-bandwidth memory interfaces, and Interlaken chip-to-chip interconnects carrying the TileLink coherence protocol. Additionally, SiFive will have demos at each event.

WHEN: Tuesday, April 9, 2019 to Thursday, April 11, 2019

WHERE: Hyatt Regenncy, Santa Clara, Calif.

About SiFive

SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit www.sifive.com.