Lowest risk, fastest path to RISC‑V. Jump start your project today.
Developed in lockstep with the RISC-V standard, SiFive’s Coreplex IP are designed for ASIC, FPGA, and other implementations. Coreplex U Series and E Series span from high-performance 64-bit RISC-V multicore Unix-capable processors to 32-bit RISC-V embedded microcontrollers, and are also customizable and extensible to your application needs.
The U5 Coreplex is the world’s most advanced 64-bit RISC-V core. Designed for high-end applications, the U5 Coreplex supports multicore, cache coherency, multi-level caches, as well as single-precision and double-precision floating-point operations in hardware. The U5 Coreplex supports Unix and other advanced operating systems and is fully compliant with the latest RISC-V privileged architecture.
- 1.6GHz+ in 28nm
- Supports RV64GC architecture
- Multicore support
- Cache coherency
- Sv39 virtual address support
- Customizable instructions and accelerators
The E3 Coreplex is the world's most efficient 32-bit RISC-V core. With optional support for RV32E, compressed mode, multiplier/divide, and floating-point, the E3 maximizes your compute options while minimizing silicon area and power. The E3 Coreplex is ideal for embedded microcontrollers needing extremely low power and efficient 32-bit computing, as well as deeply embedded control CPUs.
- Minimal area and power
- Supports RV32I/RV32E architecture
- Optional support for hardware multiplier and divider
- Optional support for compressed instructions
- Optional support for floating-point operations
- Optional support for N user-level interrupts and memory protection
- Optional support for atomic instructions