Peripheral IP
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All SiFive RISC-V Core IP comes with a native TileLink interface bus. TileLink is a high-performance scalable cache-coherent fabric that is free and open-source, just like RISC-V. We also provide bridge adapters for legacy bus protocols such as AXI4, AHB-Lite, and APB.

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Please contact us at info@sifive.com to let us know how we can help.