Designed by the inventors of RISC‑V.
RISC-V is a free and open instruction set architecture based on modern design techniques and decades of computer architecture research.
With over 60 member companies and a robust software ecosystem, RISC-V is set to be the standard architecture in all modern computing devices, from 32-bit embedded microcontrollers to 64-bit application processors and datacenter accelerators and beyond.
SiFive Core IP are the most widely deployed RISC-V cores in the world and are the lowest risk, easiest path to RISC-V. SiFive Core IP are fully synthesizable and verified soft IP implementations that scale across multiple design nodes, making them ideal for your next SoC design.
We're here to change the way you buy IP
As the inventors of RISC-V, we want to make RISC-V open and accessible to everybody.
As engineers, we want to make it super easy to learn the details of IP and painless to evaluate one.
- No NDAs
- Instant Evaluation
- Fair, No Royalty Pricing
Get immediate access to all the documentation and datasheets that you need. No registration, no NDA needed.
Benchmark your code on real hardware. Register for immediate access to FPGA bitstreams, or sign up for a free evaluation of RTL.
Changing the way people buy IP. DocuSign and download. We offer fair and transparent pricing, with a simple 7-page license.