Choose E51 RISC-V Core IP
64-bit Embedded Processor. 32-bit price, power, and area.

SiFive’s E51 RISC-V Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. An extremely small-footprint, low-power design makes the E51 ideal for devices that require a tiny system controller for housekeeping, security, or host processing within a larger 64-bit SoC. An extended memory map of 40 physical address bits also makes the E51 a great solution for SSD controllers and networking applications.

E51 RISC-V Core IP Key Features

  • Fully compliant with the RISC-V ISA specification
  • RV64IMAC Support:
    • RV64I – 64-bit RISC-V with 32 integer registers
    • Integer Multiplication and Division (M) support
    • Atomic Mode (A) support for high-performance, portable software
    • Compressed Mode (C) support for better code density
  • Machine and User Mode Support
  • In-order, 5-6 stage variable pipeline
  • Advanced Memory Subsystem:
    • 16KB, 2-way Instruction Cache
    • Instruction Tightly Integrated Memory (ITIM) option
    • Up to 64KB Data Tightly Integrated Memory (DTIM) support
  • Support for up to 40 physical address bits
  • Efficient and Flexible Interrupts:
    • Local interrupts w/ vectored addresses — up to 16
    • Platform Level Interrupt Controller (PLIC) — 511 interrupts w/ 7 priority levels
    • RISC-V Core Local Interruptor (CLINT) — 1 timer, 1 SW
  • 8-Region Physical Memory Protection (PMP)
  • High performance TileLink Interface
  • Peripheral IP available to interface to AHB-Lite, AXI4, APB
  • 1.8 DMIPS/MHz
  • 2.76 Coremark/MHz

View E51 RISC-V Core IP Manual

E51 RISC-V Core IP Block Diagram

E51 RISC-V Core block diagram

E51 RISC-V Core IP Power, Performance, and Area

28nm HPC 55nm LP
Core-Only Areaa 0.046 mm2 0.083 mm2
Core Complex Areab 0.23 mm2 0.66 mm2
Frequency Typical: 1.5 GHz
Worst: 900 MHz
Typical: 540 MHz
Worst: 320 MHz
Typical Performance 2700 Total DMIPS 972 Total DMIPS
Core-Only Powera,c 36 DMIPS/mW 15 DMIPS/mW
Core Complex Powerb,c 125 DMIPS/mW 78 DMIPS/mW
  • a Core-only data excludes SRAM; 85% utilization
  • b Core Complex data includes 16KB Instruction Cache, 16KB DTIM, PLIC, Debug; 85% utilization
  • c TT corner @ Vnom, 25C

E51 RISC-V Core IP Standard Deliverables

  • E51 RISC-V Core IP in Verilog
  • Constraints File (SDC)
  • Integration Guide covering:
    • Synthesis
    • Place and Route
    • Floorplanning
  • Test simulation environment

The Only Commercially Available 64-bit Embedded Core

E51 RISC-V Core No Comparable ARM Core
RV64IAC
M + U Modes
Unavailable.

No 64-bit Embedded Core.
Up to 1.5 GHz in 28nm
1.8 DMIPS/MHz
Physical Memory Protection (PMP)
16KB Instruction Cache
Instruction Tightly Integrated Memory (ITIM) up to 8KB
Data Tightly Integrated Memory (DTIM) up to 64KB
31 Usable Registers
511 Global Interrupts + 16 Local Vectored Interrupts
No royalties
7-page contract
Open access to all

E51 Software Tools

The E51 comes with a complete set of RISC-V tools for fast and easy software development. SiFive provides a rich SDK with demo software and an easy-to-install binary toolchain. Standard development and debug tools including OpenOCD, GDB, and an Eclipse IDE, are available for free here.

A project open in the Freedom Studio IDE