Choose U54‑MC RISC-V Core IP
Multi-Core 64-bit RISC-V Applications Processor

SiFive's U54-MC RISC-V Core IP is the world’s first RISC-V based 64-bit quad-core application processor, supporting full-featured operating systems such as Linux. The U54-MC Core’s high-performance and flexible memory system makes it ideal for applications such as AI, machine learning, networking, gateways, and smart IoT devices.

U54-MC RISC-V Core IP Key Features

  • Fully compliant with the RISC-V ISA specification
  • 4x RV64GC U54 Application Cores:
    • 32KB L1 I-cache with ECC
    • 32KB L1 D-cache with ECC
    • 8 Region Physical Memory Protection
    • 48 Local Interrupts per core
    • Sv39 Virtual Memory support with 38 Physical Address bits
  • 1x RV64IMAC E51 Monitor Core:
    • 4KB L1 I-Cache with ECC
    • 8KB DTIM with ECC
    • 8 Region Physical Memory Protection
    • 48 Local Interrupts
  • Fully Coherent TileLink Bus
  • Integrated 2MB L2 Cache with ECC
  • Real-time capabilities:
    • Both the L1 Instruction Cache and the L2 Cache can be configured into high speed deterministic SRAMs
  • CLINT for multi-core timer and software interrupts
  • PLIC with support for up to 511 interrupts with 7 priority levels
  • Debug with instruction trace
  • U54 Performance:
    • 1.7 DMIPS/MHz
    • 2.75 CoreMark/MHz

View U54-MC RISC-V Core IP Manual

U54-MC RISC-V Core IP Block Diagram

U54 RISC-V Core block diagram

U54-MC RISC-V Core IP Power, Performance, and Area

28nm HPC
Core Only Areaa 0.234mm2
Core Complex Areab 0.538mm2
Frequencyc Typical: 1.5GHz
Worst: 960MHz
  • a Single U54 Core-only data, excludes SRAM; 85% utilization
  • b Core Complex data includes single U54 core, 32KB I-Cache, 32KB D-Cache, PLIC, Debug
  • c 12 track standard cells. Typical: TT Corner @ 0.9V, 25C, Worst: Slow/Slow, 0.81V, -40C

U54-MC RISC-V Core IP Standard Deliverables

  • U54-MC RISC-V Core IP in Verilog
  • Constraints File (SDC)
  • Integration Guide covering:
    • Synthesis
    • Place and Route
    • Floorplanning
  • Test simulation environment

Compare with ARM Cortex-A35

U54-MC RISC-V Core ARM Cortex-A35
M + S + U Mode
ARMv8-A, AArch32, AArch64
16 bit instructions AArch32 only
Physical Memory Protection (PMP) and MMU None, MMU only
Real-time capable Not applicable
E51 Monitor Core Requires additional IP
Integrated interrupt controller Requires additional IP

U54-MC Software Tools

The U54-MC comes with a complete set of RISC-V tools for fast and easy software development. SiFive provides a rich SDK with demo software and an easy-to-install binary toolchain. Standard development and debug tools including OpenOCD, GDB, and an Eclipse IDE, are available for free here.

A project open in the Freedom Studio IDE