High speed chip-to-chip interface protocol with scalable bandwidth, low latency and reliable data transfer over serial links. The latest generation supports up to 1.2Tbps bandwidth with support for NRZ and PAM4 serial links.
Interlaken IP is used by many applications including NPU, traffic management and switch fabrics. Open-Silicon, a SiFive company, was a founding member of the Interlaken Alliance and supports silicon-proven Interlaken IP with over 75+ tier 1 customers on various technology and process nodes. The IP includes a validation platform supporting up to 1.2Tbps (64K channels and 48 SerDes lanes) using a wide range of transceiver speeds and Forward Error Correction (FEC) engines.
Extending on the 8th generation of its Interlaken IP core, SiFive now introduces low latency version of the Chip-to-Chip and Die-to-Die connectivity Interlaken IP used across many applications. Cutting edge technologies such as High Performance Computing (HPC) clusters, AI/ML chip clusters, IoT edge devices, networking, and switching fabrics are demanding high throughput data transfer from one chip to another at very low latency. Interlaken-LL includes a validation platform supporting up to 256Gbps.
Interlaken Controller Block Diagram
High Level Features
- Supports up to 1.2Tbps bandwidth
- Supports up to 48 SerDes lanes
- Supports SerDes from 3.125Gbps to 56Gbps
- Supports up to 64K channels
- Supports Interlaken Look Aside protocol
- Supports flow control (in band and out of band)
- Supports bifurcation & aggregation with multi-core configuration
- Supports flexible user interface options
Interlaken FEC (ILKN FEC)
Interlaken FEC (ILKN FEC) Block Diagram
High Level Features
- Supports 56G PAM4 SerDes
- Supports Interlaken protocol and Ethernet protocol
- Supports RS(544,514)
- Supports configurable alignment marker (AM)
If you already have a specific SoC IP spec in mind, our team can help you to customize controller IP as per your requirements.
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