SiFive Insight is the industry's first comprehensive pre-integrated advanced trace and debug solution for RISC-V that offers SoC designers class-leading debug capabilities to bring-up first silicon, support hardware and software integration, and debug software applications. From run-control debug, to cross-triggering, to advanced multi-core trace solutions, all SiFive Insight advanced trace and debug features are pre-integrated and verified together with SiFive’s RISC-V core IP in a single deliverable.
Every SiFive Core IP series includes run-control debug, which is accessible via JTAG, cJTAG or APB interface. The debug module has a configurable number of hardware breakpoints and external triggers that allow for SiFive cores to be halted by instruction accesses, data accesses, and external events while System Bus Access (SBA) enables the debugger to access memories without interrupting the core.
Debug Key Features
- Support for JTAG, cJTAG and APB interfaces
- Heterogeneous multi-core debug capability
- Up to 16 hardware breakpoints on instruction or data accesses
- Up to 16 external breakpoint triggers
- Option to include System Bus Access (SBA) to access memory without interrupting the core
Every SiFive Core IP series has the option to be coupled with a Nexus 5001-compliant trace encoder. Nexus 5001 has been an IEEE standard since 2003 and is well supported by the software tool ecosystem. The SiFive Insight trace encoder is highly configurable to meet application specific requirements.
Trace Key Features
- Heterogeneous multi-core trace capability
- Optional time-stamping with configurable resolution and source
- Up to 16 input and output hardware trace triggers for system-level interaction
- Support for several trace sink options: SRAM, ATB, SWT, system memory, pins
- Optional Instrumented Trace Component (ITC) to embed print statements directly into the trace stream
Heterogeneous ISA Support
A unique feature of SiFive Insight is compatibility with Arm® CoreSight™ technology. SiFive Insight enables advanced trace and debug of all processors in the system from a single probe and tool. This feature allows developers to continue to leverage their investment in software and tools in mixed-ISA SoC designs, making it simpler and easier than ever to adopt SiFive RISC-V for your next-generation design.
RISC-V Core IP
Choose from one of SiFive's silicon-proven RISC-V Standard Cores, and personalize to get the features that you want with SiFive Core Designer.