SoC IP
USB IP Subsystem
SoC IP

USB IP Subsystem

Full range of USB controllers supporting USB 2.0 / USB 3.0 / USB 3.1 gen1 and gen2 in host and device mode of operation. Supports AXI interface and in-built DMA features.

USB IP Subsystem

USB IP Subsystem

USB 3.1 Host Controller

USB 3.1 Host Controller

Details

  • Compliant with xHCI specification, USB 3.1 specification, USB 3.1 PIPE interface (Support 8/16/32 data bus width), UTMI interface(Support 8/16 data bus width), AXI, AHB Bus standards (Supports 32/64/128 bit data bus)
  • Support multiple root hub ports
  • Support multiple devices and endpoints
  • Supports many configuration options
  • Supports all USB 3 power-down modes
  • Supports all types of US transactions, including bulk streaming
  • Synchronous SRAM interface for FIFO
  • Fully integrated DMA controller

USB 3.1 Device Controller

USB 3.1 Device Controller

Details

  • Compliant with USB 3.1 Gen 2 specification, USB 3.1 PIPE interface
  • Supports 32/64 data bus width
  • AXI, AHB bus standards
  • Supports 32/64/128 bit data bus
  • Supports all USB 3.1 power down modes
  • Supports Ccontrol, bulk, Iiochronous and interrupt transactions
  • Bulk endpoint support streaming
  • Device can be configurable up to 15 IN and 15 OUT functional endpoints
  • Configurable number of function endpoints
  • Dynamically configurable endpoint FIFO for optimum usage of memory
  • Synchronous SRAM interface for FIFO
  • Fully integrated DMA controller

USB 3.2 Retimer

USB3.2 Retimer

Details

  • Compliant to USB 3.1 Appendix E standard
  • Supports Gen 1(5G) and Gen 2(10G) speeds
  • Supports all low power states
  • Supports MCU CSR interface to drive ASIC control and status register
  • Supports PCS logic with 8b/10b for Gen1 and 128b/132b for Gen2 support
  • Supports Synaptic’s SERDES interface
  • Optional support to external PHY with PIPE interface
  • SRIS architecture
  • "Pass through" and "local loopback" supported
  • Provision to monitor key events including internal errors
  • Provision to monitor link states
  • Option to tune PIPE control signal through CSR interface
  • Master loopback support for production test
  • Option to generate LFPS pattern in debug mode

PCS

PCS Functional Block Diagram

Details

  • Supports USB Gen 1(5G) and USB Gen 2(10G) speeds
  • Compliant to USB 3.1 PIPE interface
  • Supports 8b/10b for Gen1 and 128b/132b for Gen2 support
  • Supports all low power states
  • Supports MCU CSR interface to drive ASIC control and status register
  • Supports Synaptic’s SERDES interface
  • Provision to monitor key events including internal errors
  • Option to generate LFPS pattern in debug mode

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