SiFive Scalable Microarchitectures
Enabling Unprecedented Configurability
SiFive® Core IP technology enables designers to access the entire underlying microarchitecture of the CPU IP through the SiFive Core Designer web-based tool. Access to the entire parameterized microarchitecture enables designers to create the exact core needed for their application, optimizing the Power, Performance, and Area (PPA) of the design, reducing costs as well as enabling completely new use cases and business models. Beyond access to the microarchitecture of the CPU, SiFive customers have the ability to extend the design by adding custom instructions through SiFive Custom Instruction Extensions (SCIE).
This unprecedented configurability enables companies to reuse the exact same software stack and tools across multiple projects. As shown in the following examples, the compact SiFive 2 Series Core IP can be configured to hit a variety of design targets and can span the range of use cases from Cortex-M0 to Cortex-M4.
SiFive 2-Series Configurability Example
- Area Constrained Use SiFive Core Designer to configure the E2 Series Core to be as small as 13.5k Gates
- High Performance The E21 Standard core is 12% higher performance than Cortex-M4 in 80% of the area
- Balanced The E20 Standard Core is 90% of the performance of Arm* Cortex*-M3 in 60% of the area
- 64-bit MCU The S2 Series is the world’s smallest 64-bit CPU while offering ease of integration and efficient performance
Enterprise SSD Example
The ability to configure SiFive’s Core IP has enabled companies to reduce power consumption and area to a third of the nearest competitor, as evidenced by the first RISC-V enterprise SSD from FADU
- FADU Annapurna, the world’s first RISC-V SSD controller
- FADU Bravo Series Enterprise SSD
- Powered by SiFive S5
“SiFive’s RISC-V Core IP was 1/3 the power and 1/3 the area of competing solutions. and gave FADU the flexibility we needed in optimizing our architecture to achieve these groundbreaking products.”
J. Lee, FADU CEO
- FADU’s second generation RISC-V-enabled DELTA SSD Gen4 platform, targeted at High Performance OEM and hyper scale data center storage and powered by SiFive S5 RISC-V Core IP, was awarded Best of Show – Most Innovative Flash Memory Startup at the 2020 Flash Memory Summit (FMS)
- There’s more in our blog on SiFive Core IP being used in SSD controller SoCs
Wearable AI Example
Huami designed the world’s first AI-powered wearable processor – Huangshan No. 1 with integrated biometric signal processing. SiFive’s Core IP E31 enabled Huami to reduce power consumption making it more than 38 percent efficient than Arm Cortex-M4.
- Huangshan No. 1 (MHS001) from Huami
- An integrated biometric signal processor using 4 dedicated AL engines and a built-in CNN based interface engine
- 38 percent more efficient than the Arm Cortex-M4
- Powered by SiFive E3
“The world’s first artificial intelligence-powered wearable chipset”
RISC-V Core IP
Choose from one of SiFive's silicon-proven RISC-V Standard Cores, and personalize to get the features that you want with SiFive Core Designer.
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