Moore’s Law has ended.

It’s time for a paradigm shift.

For 30+ years, chips kept getting faster and cheaper. In the race to get to the next process node, there wasn't time or a need to customize. But the world has changed—compute has hit a limit and the cost of building chips keeps increasing exponentially.

The next wave of innovation is now happening at the hardware-software interface, and companies need custom silicon solutions to stay ahead. SiFive is leading the charge.

Chip Designer

Start with your idea, get it in silicon.

Chips are in everything you own. Yet until now, only the biggest players with the deepest pockets could create custom SoCs.

SiFive is changing all of that. Now, thanks to our powerful design tools, every entrepreneur, inventor and innovator can translate their dreams into silicon.

  • Differentiate using our customizable SoC IP.

    Best-in class SoC IPs covering a wide range of applications from IoT and networking to AI/HPC.

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  • SiFive’s “Idea-to-Silicon” methodology significantly reduces design time.

    Our “Idea-to-Silicon” methodology includes access to solutions for market-focused designs based on multiple configurations and integrating proven IP as well as the ability to incorporate your own IP in a complex SoC scenario. SiFive’s methodology lowers cost, saves time, and delivers a custom SoC design for your specific needs.

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SiFive Founders

We invented RISC‑V.

SiFive’s founders are the same UC Berkeley professor and PhDs who invented and have been developing the RISC‑V Instruction Set Architecture (ISA) since 2010.

RISC‑V is a free and open ISA designed for today’s software stacks. Rapid industry-wide adoption has poised RISC‑V to be the new standard for compute.

Group protrait of the three founding members of SiFive

Andrew Waterman

Co-Founder & Chief Engineer

Yunsup Lee

Co-Founder & Chief Technology Officer

Krste Asanovic

Co-Founder & Chief Architect

Core Designer

Customize your RISC-V core.

SiFive Standard Cores are the most silicon-deployed RISC‑V solutions in the world. From low-power embedded microcontrollers to multi-core applications processors, our core IP is the lowest risk, easiest path to RISC-V.

SiFive Standard Cores are customizable and can be tuned to meet precise needs with the SiFive Core Designer.

Free evaluation Dev Kits with Verilog RTL and FPGA bitstreams are available to download now.

Here's how it works.

  • 01. Design

    Customize a SiFive Standard Core to meet the precise needs of your product.

  • 02. Evaluate

    Simulate with fully-functional, synthesizable Verilog RTL. Run your application code on an FPGA.

  • 03. License

    Licensing is straightforward and your custom RISC-V core IP is available within weeks.

What People
are Saying

RISC‑V offers a fresh approach that has the potential to help reduce SoC development time and cost significantly.

Raja Koduri — GM Edge Computing Solutions, Chief Architect, Intel