• Intel Capital Investment Boosts Vision for the Future
    Naveed Sherwani, Chief Executive Officer at SiFive, May 8, 2018

    We’re very happy to announce that Intel Capital participated in our recent Series C funding round. The investment was revealed at the Intel Capital Global Summit earlier today.

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  • RISC-V QEMU Part 2: The RISC-V QEMU port is upstream
    Michael Clark, April 25, 2018

    QEMU 2.12.0 was released on April 24th 2018 and this version is the first official QEMU version to contain the RISC-V port. This is yet another milestone towards the development of the Open Source RISC-V tools on top of the recent acceptance of RISC-V in Linux kernel 4.15 in December last year and GLIBC 2.27 this past February.

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  • Dover Microsystems Brings Real-Time Chip Security to SiFive’s DesignShare
    Shafy Eltoukhy, head of DesignShare, April 17, 2018

    Boy have we been busy. Over the last few months, our DesignShare ecosystem has continued to expand, and, this week, we were excited to welcome Dover Microsystems into the program.

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  • The SiFive Download - The Next Revolution is Here!
    Jack Kang, vice president of product marketing, SiFive, April 16, 2018

    First, we are thrilled to have recently announced that we raised $50.6 million in our Series C funding round! We wanted to thank our existing and new investors - including Chengwei Capital, Huami, SK Telecom and Western Digital - for the continued support and new engagement, so we held a party to celebrate!

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  • The SiFive Download - Are you ready to UNLEASH your genius?
    Jack Kang, vice president of product marketing, SiFive, March 6, 2018

    We’re heading to the Embedded Linux Conference next week, March 12-14, to hold our first hackathon. Developers will be among the first to run code on the HiFive Unleashed board with a chance to take home a board of their own and win a $1,000 cash prize.

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  • All Aboard, Part 11: RISC-V Hackathon, Presented by SiFive
    Palmer Dabbelt, March 3, 2018

    Date: Monday, March 12 – Wednesday, March 14 Time: 10:30am Monday – 1:00pm Wednesday Location: Embedded Linux Conference, Hilton Portland Downtown, Skyline II, Floor 23

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  • Welcome Aboard, Sunil Shenoy!
    Allen Leibovitch, Marketing, SiFive, March 1, 2018

    As our business continues to grow, the people we hire continue to impact and shape our business more and more.

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  • All Aboard, Part 10: How to Contribute to the RISC-V Software Ecosystem
    Palmer Dabbelt, February 20, 2018

    We recently announced the HiFive Unleashed, a development board for Freedom U540-C000, the world’s first Linux-capable RISC-V ASIC. The announcement of this board roughly lined up with the first upstream releases of Linux and glibc that contain RISC-V support. As a result, our news has driven a lot of interest from the open source software community – that was really the whole point of announcing the board in the first place, so in that sense it’s working out very well.

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  • The SiFive Download - Ringing in 2018 with Fresh Faces and Big Resolutions
    Jack Kang, vice president of product marketing, SiFive, January 23, 2018

    Before we dive into our newsletter, we want to take a moment to talk about the vulnerabilities around Meltdown and Spectre. First off – and most fortunately – SiFive’s RISC-V Core IP offerings are not affected by Meltdown and Spectre. Secondly, as the RISC-V Foundation’s statement on these vulnerabilities notes, now is the time for open architecture and open hardware designs to shine.

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  • SiFive Statement on Meltdown and Spectre
    Andrew Waterman, Co-Founder and Chief Engineer at SiFive, January 5, 2018

    The recently disclosed speculation-based timing attacks Meltdown and Spectre have received much attention this week—and rightly so. The vulnerabilities these attacks exploit are not limited to a particular instruction-set architecture, nor are they restricted to a single vendor’s implementations. Many processors that rely upon speculation to improve performance are affected, even some that do not use out-of-order execution.

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  • A Look Back: 7th RISC-V Workshop
    Allen Leibovitch, Marketing, SiFive, January 3, 2018

    A new year brings new opportunities. Before we dive into 2018, we wanted to take some time to reflect on some of the excitement we experienced over the last couple of months.

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  • RISC-V QEMU Part 1: Privileged ISA v1.10, HiFive1 and VirtIO
    Michael Clark, December 20, 2017

    This post covers recent development in RISC-V QEMU, the open source machine emulator and virtualizer. We’ve been playing a game of catch-up with the hardware folks so that we can match the capabilities of the Freedom U500 SDK. We’re not quite there yet, but we’ve made some important improvements that will allow for a more usable emulator.

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  • All Aboard, Part 9: Paging and the MMU in the RISC-V Linux Kernel
    Palmer Dabbelt, December 11, 2017

    This entry will cover the RISC-V port of Linux’s memory management subsystem. Since the vast majority of the memory management code in Linux is architecture-independent, the vast majority of our memory management code handles interfacing with our MMU, defining our page table format, and interfacing with drivers that have memory allocation constraints.

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  • All Aboard, Part 8: The RISC-V Linux Port is Upstream!
    Palmer Dabbelt, December 5, 2017

    As some of you may have heard, the RISC-V Linux port has been accepted into Linus’ tree and is slated to release as part of 4.15. While this is a major milestone, we’re far from done in Linux kernel land and there’s a whole lot of work left to be done in userspace.

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  • A New Season, New Partnerships and a New Frontier - The SiFive Download, Part IV
    Jack Kang, vice president of product and business development, SiFive, November 30, 2017

    These last few months have been equal parts busy, exciting, and promising. We are eager to catch you up on the latest happenings at SiFive and within the RISC-V ecosystem as a whole.

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  • Awards Season Brings Big Surprises
    Jack Kang, vice president of product and business development, SiFive, November 16, 2017

    It’s that time of year again–awards season, the time when companies submit their best-of-year products and initiatives for consideration by industry watchers and judging panels. It’s a familiar, fairly predictable cycle, but sometimes it can take one by surprise.

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  • Analog Bits Clocks into the DesignShare Ecosystem
    Jack Kang, vice president of product and business development, SiFive, November 15, 2017

    Our DesignShare family is growing, and we’re thrilled to announce that Analog Bits, the industry’s leading provider of low-power mixed-signal IP solutions, is now a part of the ecosystem.

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  • The DesignShare Ecosystem Expands Its Catalog of IP to include eMemory’s Logic NVM
    Jack Kang, vice president of product and business development, SiFive, November 9, 2017

    It’s been a fantastic few months for us with new initiatives and industry recognitions, and we’re excited to share more great news. Earlier this month, we welcomed eMemory, the IP provider of logic-based, non-volatile memory (Logic NVM), as the latest company to join the DesignShare movement!

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  • All Aboard, Part 7: Entering and Exiting the Linux Kernel on RISC-V
    Palmer Dabbelt, October 23, 2017

    Continuing our journey into the RISC-V Linux kernel port, this week we’ll discuss context switching. Context switching is one of the more important parts of an architecture port: it is all but impossible to completely abstract away the details of entering and exiting the kernel, Since this is on many critical paths (system calls and scheduling) it must go fast, but since it’s the one line of protection the kernel has from userspace it must also be secure.

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  • A Core By Any Other Name...
    Jack Kang, vice president of product and business development, SiFive, October 11, 2017

    With all apologies to Shakespeare, would a core by any other name still hit the sweet spot in the market for those looking for cost-effective custom silicon?

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  • Welcome - The SiFive Download, Part III
    Jack Kang, vice president of product and business development, SiFive, October 10, 2017

    Earlier this month, we took a huge step in democratizing access to custom silicon when we unveiled our newest core, the U54-MC Coreplex - the industry’s first RISC-V based, 64-bit, quadcore application processor with support for full featured operating systems including Linux, Unix and FreeBSD.

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  • All Aboard, Part 6: Booting a RISC-V Linux Kernel
    Palmer Dabbelt, October 9, 2017

    This post begins a short detour into Linux land, during which we’ll be discussing the RISC-V Linux kernel port. SiFive has recently announced the Linux-capable U54-MC RISC-V Core IP, and our Linux port was recently submitted to linux-next, Linux’s staging branch, so assuming that everything goes smoothly we should be merged at the end of the next merge window. Along with Linux we should soon have the full suite of core system components upstream, both for embedded systems (via binutils, GCC, and newlib) and larger (via binutils, GCC, glibc, and Linux).

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  • Introducing the U54-MC RISC-V Core IP – The First RISC-V Core with Linux Support
    Jack Kang, vice president of product and business development, SiFive, October 6, 2017

    Since we launched the industry’s first open-source RISC-V SoC back in July of last year, we’ve had the pleasure of pushing the boundaries of the RISC-V ecosystem and have been delighted by the support that SiFive – and RISC-V – has gained from system designers and Makers alike.

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  • All Aboard, Part 5: Per-march and per-mabi Library Paths on RISC-V Systems
    Palmer Dabbelt, September 18, 2017

    A previous blog described how the -march and -mabi command-line arguments to GCC can be used to control code generation for the sources you compile as a user, but most programs require linking against system libraries in order to function correctly. Since users generally don’t want to compile every library along with their program, either because they’re too complicated or because they’re meant to be shared, a mechanism is needed for linking against the correct set of system libraries to match the ISA of the user’s target system and the ABI of the user’s generated code.

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  • The DesignShare Ecosystem Grows with the Addition of UltraSoC’s Embedded Analytics IP
    Jack Kang, vice president of product and business development, SiFive, September 12, 2017

    It’s been a busy summer for us. Our days have been filled with many prospect, customer and partner meetings with teams looking to leverage RISC-V in their roadmap. Last week, we announced the outcome of one of those meetings: UltraSoC, a provider of on-chip monitoring and analytics IP, is the latest company to join the DesignShare movement.

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  • RISC-V 101 Webinar
    Jack Kang, vice president of product and business development, SiFive, September 12, 2017

    This one-hour webinar is for Embedded Developers who are interested in learning more about the RISC-V architecture. It covers areas such as the Register File, Instruction Types, Modes, Interrupts, and Control and Status Registers. Prior knowledge of RISC-V is not necessary, but having a basic understanding of Computer Architecture is beneficial.

    Watch it

  • All Aboard, Part 4: The RISC-V Code Models
    Palmer Dabbelt, September 11, 2017

    The RISC-V ISA was designed to be both simple and modular. In order to achieve these design goals, RISC-V minimizes one of the largest costs in implementing complex ISAs: addressing modes. Addressing modes are expensive both in small designs (due to decode cost) and large designs (due to implicit dependencies). RISC-V only has three addressing modes:

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  • Welcome - The SiFive Download, Part II
    Jack Kang, vice president of product and business development, SiFive, August 29, 2017

    On August 15, we announced that regarded industry veteran Naveed Sherwani has joined SiFive as CEO. We invited him to share his vision for the company and his optimism for fomenting a revolution in the semiconductor industry.

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  • All Aboard, Part 3: Linker Relaxation in the RISC-V Toolchain
    Palmer Dabbelt, August 28, 2017

    Last week’s blog entry discussed relocations and how they apply to the RISC-V toolchain. This week we’ll be delving a bit deeper into the RISC-V linker to discuss linker relaxation, a concept so important it has greatly shaped the design of the RISC-V ISA. Linker relaxation is a mechanism for optimizing programs at link-time, as opposed to traditional program optimization which happens at compile-time. This blog will follow an example linker relaxation through the toolchain, demonstrate an example of how linker relaxations meaningfully improve the performance of a real program and introduce a new RISC-V relocation. We’ll shy away from discussing the impact of linker relaxations on the RISC-V ISA, until another blog entry.

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  • Our New Partnership with Rambus and the DesignShare Economy
    Jack Kang, vice president of product and business development, SiFive, August 24, 2017

    As we continue to expand our product offerings to better serve the rapidly growing RISC-V and SiFive community, we are always looking to work with companies (big and small) who share our vision.

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  • All Aboard, Part 2: Relocations in ELF Toolchains
    Palmer Dabbelt, August 21, 2017

    Our first stop on our exploration of the RISC-V toolchain will be an overview of ELF relocations and how they are used by the RISC-V toolchain. We’ll shy away from discussing linker relaxations and their impact on performance for a follow-up blog post so this doesn’t get too long. The example has been carefully constructed to be unrelaxable as to avoid confusion. Additionally we’re only going to discuss the relocations used by statically linked executables, avoid discussing position independent executables and forget about thread local storage – like linker relaxation, all of those warrant a whole post on their own. There will be a lot more to come about relocations in later blog posts.

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  • All Aboard, Part 1: The -march, -mabi, and -mtune arguments to RISC-V Compilers
    Palmer Dabbelt, August 14, 2017

    Before we can board the RISC-V train, we’ll have to take a stop at the metaphorical ticket office: our machine-specific GCC command-line arguments. These arguments all begin with -m, and are all specific to the RISC-V architecture port. In general, we’ve tried to match existing conventions for these arguments, but like pretty much everything else there are enough quirks to warrant a blog post. This blog discusses the arguments most fundamental to the RISC-V ISA: the -march, -mabi, and -mtune arguments.

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  • All Aboard, Part 0: Introduction
    Palmer Dabbelt, August 7, 2017

    I’m Palmer Dabbelt, a software engineer at SiFive and a maintainer of various RISC-V ports. I’ve been working with the RISC-V ISA for a few years, and it’s finally starting to get ready for prime-time. We’re not yet upstream in Linux or glibc, but hopefully by the end of the year we’ll have the core set of system software in the relevant upstream repositories – at which point distributions can begin porting to RISC-V and users can begin using our software. I started working with RISC-V before the user ISA had been finalized (at least v2 of the user ISA, the real one :)) and it’s almost a bit scary how real things have gotten over the last few years.

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  • The SiFive Download: A Year in Review
    Jack Kang, vice president of product and business development, SiFive, July 11, 2017

    Welcome to the first iteration of our bi-monthly newsletter, The SiFive Download! On a regular cadence, we will plan to give you a download on all things SiFive – from the events we will be attending to the articles we’ve been featured in. This newsletter is intended to give you a glimpse under the SiFive hood.

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  • The FE310 is in a Museum – Which is Pretty Cool
    Jack Kang, vice president of product and business development, SiFive, June 14, 2017

    It’s been quite busy the past month and change for SiFive and the RISC-V community. On May 4, we unveiled our RISC-V Core IP, radically redefining the process by which you can license and buy custom IP. The RISC-V Core IP launch was followed by a panel at Maker Faire Bay Area, where we got to chat with American computer engineering pioneer Dave Patterson and other panelists about RISC-V and the future of open-source hardware (pictured below).

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  • SiFive; the journey to becoming the easiest company to do business with!
    Sander Arts, May 7, 2017

    Last week, SiFive announced the immediate availability of its RISC-V Core IP, the fastest and easiest way to license RISC-V cores. It sounds like another announcement from another tech company. However, it isn’t if you read the press release that was sent out to the world. I think Yunsup Lee, CTO and co-founder of SiFive explains it well in there:

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  • RISC-V GCC is upstreamed!
    Andrew Waterman, March 3, 2017

    I’m thrilled to announce a milestone in RISC-V’s adoption within the open-source software community: GCC, the popular compiler for GNU/Linux systems, has accepted the RISC-V backend for inclusion in its next release. We expect GCC 7.1 will ship with RISC-V support in late April. A robust compiler underpins nearly all other software development, and so I expect the availability of the GCC port will accelerate the development of applications, runtime libraries, and operating systems for RISC-V.

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  • Women in Open Source: You DO Belong Here
    Megan Wachs, February 8, 2017

    Hi. I’m Megan. And I’m a woman working on RISC-V hardware.

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  • Stronger Together – Collaborating with OnChip to Expand the Open-Source Hardware Ecosystem
    Jack Kang, January 26, 2017

    Here at SiFive, we believe that open-source and mass customization are going to change the semiconductor industry. While working with open-source software is well understood by (most) companies and individuals, open-source hardware is still a new concept.

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  • The Alternative That Continues to Matter
    Andrew Waterman, Co-Founder and Chief Engineer at SiFive, January 19, 2017

    SiFive was founded on one simple belief: that open source and mass customization are the answer to the end of conventional transistor scaling and escalating chip design costs. The free and open RISC-V ISA has been central to our vision of enabling a whole new range of applications for everyone — even the smallest company, inventor or maker. We wanted to free silicon — and we firmly believed that RISC-V was the critical first step.

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  • Custom Chips For Under $100K
    Jack Kang, December 20, 2016

    It was exciting to see how much activity has developed around RISC-V and SiFive at the recent 5th Workshop here in Silicon Valley. No doubt there’s still work to be done, but the ecosystem has come such a long way in the past 12 months. Once again, the workshop was sold out! More than 350 attendees, 107 companies and 20 universities were represented, and those people were all in awe when they saw SiFive’s real silicon come out with the message that SiFive is open for MORE business. The community also was impressed that we made open-source RTL code available online for our Freedom SoCs. All this news marked a milestone for a still nascent open-source hardware movement.

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  • The Best “Three-Month Project” Ever
    Yunsup Lee, Co-Founder and CTO at SiFive, November 29, 2016

    A couple weeks ago, Jack and I traveled to Taiwan. Not that unusual for those of us in the semiconductor industry used to making a pilgrimage to visit customers and partners. This trip, however, was big for us, and we brought back the best “souvenirs” ever – the first ever commercially available RISC-V SoCs!

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  • An Ace Up Our Sleeve?
    Jack Kang, November 9, 2016

    In a recent post, Yunsup shared some of the successes and challenges we’ve faced in our first year as SiFive. Little did we know when that post went live, we’d be able to follow it up with yet another measure of success: Late last week, we learned that SiFive has been shortlisted as a finalist for UBM’s ACE Award for Startup of the Year!

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  • A Year in Good Company
    Yunsup Lee, Co-Founder and CTO at SiFive, November 3, 2016

    San Francisco, Brannan Street. While Giants fans pour out of AT&T Park, SiFive employees walk out of the office after another long day of coding. Building a startup isn’t glamorous, and it’s understood that only those who put in the hard work and extra effort will make it through.

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  • Don’t Fall for an Old-Fashioned Tech Con Job
    Jack Kang, October 25, 2016

    Having worked in the semiconductor industry for over 12 years, I’ve learned one universal truth: IP companies can be notoriously difficult to work with. Unless you are one of the larger chipmakers, you’ll likely find that IP firms simply won’t make time for your design.

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  • Why The Time is Right for Open Source Hardware and ‘Chips as a Service’
    Sander Arts, September 20, 2016

    The open source software movement has been credited as a key driver of the birth of the Internet Age. Without developments such as Linux; the free Apache Web-server platform; and tools such as Java, Perl and Ruby, the Web as we know it would likely not have been possible.

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  • Why Open Source is the New Way to Build Silicon
    Stefan Dyckerhoff, August 10, 2016

    It’s no secret the semiconductor industry is in a state of flux and consolidation. As a New York Times’ headline recently screamed, “Semiconductor Industry Shrinks Some More With Latest Deal.” In the month of July alone: Analog Devices snapped up Linear Technology; Cypress closed its acquisition of Broadcom’s IoT assets; Infineon bought Wolfspeed. And then there was the deal of all deals – SoftBank acquired ARM.

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