ProductsSiFive Core IPPerformanceIntelligenceEssentialSiFive Core DesignerSoftwareBoardsSoC IPCustom SiliconDocumentationCustomer Support
Palmer Dabbelt—September 07, 2018
Last Week in RISC-V: Sept 7, 2018
This is the last version of "Last Week in RISC-V" that I plan on sending to the various mailing lists, as we'll be posting the rest of them on SiFive's Blog. I didn't get any contributions, but I also haven't gotten through my email yet -- sorry if I missed anything that's been sent it, but I'm not too far behind so I should have everything read from this week by the end of next week.
On Tuesday I tagged my pull request for Linux 4.19-rc3, which contains what I hope to be the final RISC-V patch for 4.19. The patch itself is fairly boring: it just removes some broken and obsolete code related to our initramfs support that causes initramfses to start working on RISC-V systems. The exciting part here is that this was found by Guenter Roeck while he was bringing up his CI system, which means we now have CI running on RISC-V Linux targets!
It's now time to start testing Linux 4.19 on RISC-V systems, let's see if we can shake out whatever bugs are there before the release.
Support for IMAC Systems in Linux
The RISC-V glibc port has supported ABIs without floating-point units since our original patch submission, but we have yet to properly support these systems natively in Linux due to a handful of problems with our port. Alan Kao from Andes recently published version 7 of his patch set that enables support for systems without the F or D extension in our Linux port.
Since these are fairly major patches and we're outside the merge window
I've added them to our
linux-next branch, which means they should get
merged during the 4.20 merge window in about 6 weeks. If anyone is
interested in testing them out on FPU-free hardware (real or emulated)
now is a good time. I'll let the patches bake for a bit before merging
GNU Tools Cauldron Trip Report
I'm attending the GNU Tools Cauldron in Manchester this weekend, and while we've only been through the first few sections it's already been great so far. The pair of RISC-V events, a general BoF as well as a vector specific one, went well. Attendees of the cauldron have been fairly receptive to RISC-V as an ISA -- we've crossed that hurdle where people generally now know what RISC-V is, which is great.
The vector extension talk was particularly timely, as it's starting to become time to begin work in earnest on a GCC implementation of the RISC-V vector extension. While we're a bit of a way off from having a finalized V extension we at least do know that there's a fairly significant amount of work to be done in the toolchain to fully support the RISC-V vector extension.
HiFive Unleashed Bootloader Release
Thanks to a bunch of hard work from Troy, we have officially released an open source of the first two bootloader stages that come on the HiFive Unleashed board. More info can be seen in Troy's blog post, along with a competition to reproduce the exact binary of the zero-stage bootloader in the mask ROM on the FU540-C000.
It's a timely release as well: I'm at the GNU Tools Cauldron today, and when I was asked if we were planning on releasing the bootloader source I could finally say "yes"!