SiFive - November 29, 2016

The Best “Three-Month Project” Ever

A couple weeks ago, Jack and I traveled to Taiwan. Not that unusual for those of us in the semiconductor industry used to making a pilgrimage to visit customers and partners. This trip, however, was big for us, and we brought back the best “souvenirs” ever – the first ever commercially available RISC-V SoCs!

This morning, we announced the availability of the open-sourced Freedom Everywhere 310 (FE310) SoC and HiFive1, a companion development kit.

The FE310 is the first member of the Freedom Everywhere family of customizable SoCs. Designed for microcontroller, embedded, IoT, and wearable applications, the FE310 features SiFive’s E31 RISC-V Core, a high-performance, 32-bit RV32IMAC core. Running at 320+ MHz, the FE310 is among the fastest microcontrollers in the market.

Additional features include a 16KB L1 Instruction Cache, a 16KB Data SRAM Scratchpad, hardware multiply/divide, a debug module, one-time programmable non-volatile memory (OTP), flexible clock generation with on-chip oscillators and PLLs, and a wide variety of peripherals including UARTs, QSPI, PWMs, and timers. Multiple power domains and a low-power standby mode ensure a wide variety of applications can benefit from the FE310.

What’s even more exciting is that the FE310 is the first open-source RISC-V SoC available in the industry. SiFive has contributed the FE310 RTL code to the open source community. That means you can see what’s inside the chip and completely understand how the hardware works.

Take a look: SiFive GitHub

By releasing the RTL code, we want to encourage open source development of both software support for RISC-V as well as promote open hardware development.

Personally, I couldn’t be more thrilled or proud of the team’s hard work to hit this milestone. As part of the team who’s worked on RISC-V from its earliest days (back in 2010 when we embarked on a “three-month project” to identify alternate architectures for academic research), I must say it’s a dream come true to see a commercial RISC-V chip.

As the industry’s first commercial silicon based on the free and open RISC-V ISA, FE310 represents a milestone in the growth of the RISC-V ecosystem. As Krste puts it, “The FE310 is a major step forward in the movement toward open-source and mass customization, and SiFive is excited to bring the opportunity for innovation back into the hands of system architects.”

If launching our newest product and a development kit wasn’t enough, we’re also busy this week presenting four sessions at the upcoming RISC-V Workshop:

  • “SiFive FE310 and Low-Cost HiFive1 Development Board,” Jack Kang on Tuesday at 9:30 a.m.
  • “RISC-V Technical Committee Update,” Yunsup Lee (me!) on Tuesday at 2:30 p.m.
  • “Free Chips Project: A nonprofit foundation for hosting open-source RISC-V implementations, tools, code,” Yunsup Lee (also me!) on Tuesday at 2:45 p.m.
  • “’V” Vector Extension Proposal,” Krste Asanovic on Wednesday at 9:30 a.m.

If you’re attending the Workshop, please come say “hi!” and see a demo of the HiFive1 board. The event’s sold out so if you can’t attend, you’ll have to wait until the proceedings are posted after the event. Or come see us at Booth No. 1522 at ESC Silicon Valley next week.