SiFive - June 25, 2019
When Hardware Roadmaps Look Like Software Roadmaps
The traditional cadence for microarchitecture updates is usually tied to process technology nodes or ground-up redesigns. The SiFive Core IP portfolio offers scalable microarchitectures from efficient application multi-core processors capable of running Linux, to tiny, power-sipping cores suitable for the most area constrained design points. The SiFive quarterly update program delivers key improvements, new features, and more capabilities to SiFive Core IP in a measured, methodical way. Here’s all the information you need on the SiFive Core IP Series and the latest updates!
Since launching the 2 Series in June of 2018 (see: SiFive Unveils E2 Core IP Series for Smallest, Lowest Power RISC-V Designs), it has quickly become our most popular Core Series. This quarter we have made a number of enhancements that will make the 2 Series even better!
The biggest update being the introduction of the S2 Series, the world's smallest commercial 64-bit embedded core. The S2 greatly simplifies integration of small management cores into larger 64-bit SoCs with its ability to directly address a large address space.
Speaking of small, this quarter’s release also brings support for the RV32E RISC-V standard to the E2 Series. RV32E reduces the integer register-file of a RISC-V CPU from 32 integer registers to just 16 integer registers. The RV32E option can reduce area by up to 25% on the already small E2 series while only having a marginal impact on most benchmarks. Adopting the RV32E standard allows for area conscious E2 cores to be configured as small as 13.5k gates.
We are also introducing an optional μInstruction Cache on the 2 Series allowing for higher and more efficient performance in memory-constrained designs, such as those with off-chip serial flash. This option is available on both the E2 and S2 Core Series.
The 7 Series has been well-received since being launched in October of 2018 (see: SiFive Core IP 7 Series Creates New Class of Embedded Intelligent Devices Powered by RISC-V), when it set the bar for performance of in-order cores. Thanks to optimizations in both the hardware and the compiler, performance in the popular Coremark benchmark has been increased from 4.9 Coremarks/MHz to 5.1 Coremarks/MHz, further raising the bar.
In addition to benchmark improvements, we have also added a number of features to the E7 and S7 memory subsystems. Fast IO option enables better IO throughput by optimizing the 7 Series pipeline for memory mapped operations over max frequency and cached data operations. The Data Local Store (DLS) gives the 7 Series data bus quick access to local, but globally addressable, memory which can exist in addition to a data cache or DTIM.
Lastly we brought an ITIM, directly and globally addressable Tightly Integrated Memory on the instruction bus, to the 7 Series which is instantly accessible by the core. The 7 Series ITIM can be paired with an L1 Instruction Cache, which now also has a special minimal configuration for applications mainly requiring directly-addressed memory such as that provided by the ITIM and DTIM.
SiFive Custom Instruction Extension (SCIE)
At the heart of RISC-V is the ability to build customized, application-specific features on top of the well-defined base ISA in order to meet application-specific requirements, while still maintaining compatibility with the rapidly-expanding RISC-V software ecosystem. SCIE gives SiFive customers the ability to quickly and easily add custom instructions to all SiFive Core IP offerings using Verilog and familiar workflows. SCIE also takes care not to break compatibility with the RISC-V ecosystem by taking advantage of the custom-0 and custom-1 opcode space provided by the RISC-V ISA.
At SiFive we care about the entire user experience, from the performance of our offering to the ease of use. One of the things that makes SiFive’s design process unique is the Silicon as a Service offering SiFive Core Designer (SCD). Using SCD via the easy-to-use web interface, our customers can quickly explore the design space of our Core IP offerings and download designs ready for synthesis and software benchmarking on FPGAs. Learn more about what is new with the SiFive Core Designer and the Freedom Tools Suite updates.