VIU7 Series

VIU75-MC

The SiFIve Intelligence VIU75-MC Standard Core is a high performance, multi-core RISC-V application processor with vector extensions, capable of supporting full-featured operating systems such as Linux. The VIU75-MC has 4x 64-bit VIU75 cores and 1x 64-bit S7 core. providing high performance with hard real-time determinism.

This VIU75-MC is ideal for applications requiring high-throughput performance with real-time guarantees (e.g., Vision and Machine Learning, Natural Language Processing, SLAM Processors, Sensor Fusion).

VIU75-MC Key Features
  • Base core derived from SiFive U7 series
    • RV64GCV ISA with Sv39 or Sv48 support
    • 8-stage dual-issue in-order pipeline with decoupled vector unit
    • Machine, Supervisor, and User privilege modes
    • Full TLB-based MMU for Linux-based environments
    • Single and Coherent multi-core IP platform options
  • RISC-V Vector ISA extensions v1.0
    • Floating-point, fixed-point, and integer data types
    • Vector computation up to 256b/cycle on 8b to 64b datatypes
  • Other key attributes support
    • Configurable S7 core(s) can support System boot/monitor, Sensor Hub/Fusion, and Security Co-Processor
    • Private L2$ per core, optional shared L3$
    • Up to 16 PMP regions with 4KB granularity
    • Supports SiFive WorldGuard security
    • Leverages existing SiFive Insight Advanced Trace & Debug hardware solutions

VIU75-MC Development Kit

Dev Kit Deliverables

  • RTL Evaluation
  • Test Bench RTL
  • Software Development Kit
  • FPGA Bitstream
  • Documentation
VIU7
Series Overview

VIU7 Series

The VIU7 Series features SiFive’s maximum performance RISC-V Linux-capable application processor. The VIU7 core has a 3 issue out-of-order superscalar with support for virtual memory. The VIU7 Series provides unprecedented scalability and is optimized for the highest performance per watt. This makes it ideal for applications such as edge compute, 5G base stations and AR/VR/MR.

VIU7 Series Highlights

Key Features

  • Fully-compliant with the RISC-V ISA specification
  • Up to 8+1 coherent high-performance RISC-V application processors
  • Supports an in-cluster coherent combination of application processors with real-time processors (U and S cores)
  • Low latency composable caches
  • Application processors with deterministic response
  • High -performance L1 memory microarchitecture
  • Physical memory protection
  • Custom instructions via SCIE for workload- specific customizations
  • Mixed precision floating point unit capability
  • Private cache /cache locking capability for mission critical computing

Applications

  • Enterprise Switching/Routing/Storage, Smart NICs
  • Edge Analytics, Big-Data Analytics
  • Autonomous Machines
  • Edge Compute
  • 5G Infrastructure/Base Stations
  • AR/VR/MR/XR

All Standard Cores

Area
Standard Cores
ARM Comparison
E2 Series
M0, M0+, M3, M4, M23, M33
E3 Series
R4, R5
E7 Series
M7, R7, R8
S2 Series
***
S5 Series
R4, R5
S7 Series
M7, R7, R8
U5 Series
A5, A7, A35, A53
U7 Series
A55
VIU7 Series
A55
U8 Series
A72, A73
Core Evaluation

From idea to reality.

Ready to see your code in action? The VIU75-MC Development Kit enables free evaluation of SiFive RISC-V Core IP.

Key Deliverables

Evaluation RTL

  • Full-Functional, synthesizable Verilog RTL
  • Run it in your own simulator
  • Simple, no-cost evaluation license
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