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Hackaday

At the Linley Processor Conference today, SiFive, the semiconductor company building chips around the Open RISC-V instruction set has announced the availability of a quadcore processor that runs Linux. We’ve seen RISC-V implementations before, and SiFive has already released silicon-based on the RISC-V ISA. These implementations are rather small, though, and this is the first implementation designed for more than simple embedded devices.

SiFive

SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of U54-MC Coreplex IP, the industry’s first RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux. The free and open RISC-V architecture, which is supported by an ecosystem comprising more than 70 companies, has seen tremendous growth in the embedded segment. The release of the U54-MC Coreplex marks the architecture’s expansion into the application processor space – opening entirely new use cases for RISC-V.

SiFive

SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced it has joined the TSMC (NYSE: TSM) IP Alliance Program, part of the TSMC Open Innovation Platform®, which accelerates innovation in the semiconductor design community. As an alliance member, SiFive’s RISC-V based Coreplex IP are made available to its customers to reduce time-to-market, increase return on investment and reduce waste in the manufacturing process.

SiFive

SEGGER Microcontroller, a leading supplier of software, hardware and development tools for embedded systems, and SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of SEGGER J-Link support for SiFive Coreplex IP, based on the RISC-V architecture. The growing interest in Coreplex IP is increasingly prompting vendors like SEGGER to make its industry leading tools available as part of the RISC-V ecosystem.

Cadence

The SiFive business model is that lots of people are locked out of silicon. SiFive can do custom design and deliver chips. “We believe we can do it cheaper, quicker and more predictably than anyone else.” They have also been getting lots of calls to help with designs. Growing the RISC-V ecosystem is a big opportunity. The traditional semiconductor business models take a lot of resources, so you have to pick the winners. But there aren’t any $1B sockets anymore, so you can’t easily pick the winners. The market is fragmented. SiFive wants to give everyone a chance. In a bit more detail, they will do a customer microcontroller platform and deliver 100 or so chips for under $100K.

SemiEngineering

One of the lessons learned years ago in the open-source Linux world is that free software isn’t always good enough. Consequently, being able to add commercial value around freeware can turn into a lucrative business. Enter SiFive, a startup that has been building customized platforms based on the RISC-V CPU. Started by the creators of the RISC V instruction set architecture (ISA), the company’s stated goal is to shake up the economics of the chip industry.

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Media Inquiries

For media inquiries, please contact:

Leslie Clavin
SHIFT Communications for SiFive
(415) 591-8440
lclavin@shiftcomm.com