Getting Started with SiFive IP
Part I: RISC-V 101
This webinar provided an introduction to RISC-V, covering areas such as the Register File, Instruction Types, Modes, Interrupts, and Control and Status Registers. Prior knowledge of RISC-V is not necessary, but having a basic understanding of Computer Architecture would be beneficial.
Field Engineer at SiFive, Inc.
Drew has worked in the semiconductor industry for over 10 years in various engineering and customer facing roles. At SiFive Drew is responsible for a variety of tasks including customer support, software and development tools, ecosystem development, documentation, and whatever makes the customer experience great.
Chief Architect at SiFive, Inc.
In addition to serving as Chief Architect at SiFive, Krste is a Professor in the EECS Dept. at the UC, of California, Berkeley, where he also serves as Director of the ASPIRE Lab. Krste leads the RISC-V ISA project at Berkeley, and is Chairman of the RISC-V Foundation. He is an ACM Distinguished Scientist and an IEEE Fellow. Krste Received a PhD from UC Berkeley and a BA from the University of Cambridge.
SiFive was founded by the creators of the free and open RISC-V architecture as a reaction to the end of conventional transistor scaling and escalating chip design costs.
Part II: Introduction to SiFive RISC-V Core IP
This webinar focused on embedded developers who are interested in learning more about the RISC-V architecture. Part two introduced the SiFive RISC-V Core IP Products; the E31 RISC-V Core IP and the E51 RISC-V Core IP.
Part III: Evaluating SiFive RISC-V Core IP
This webinar is for embedded developers who are interested in learning more about the RISC-V architecture. Part 3 walked users through downloading and evaluating SiFive RISC-V Core IP, including E31 Evaluation RTL, and using Freedom Studio to program and debug code running on the E31 FPGA evaluation.