Part III: Evaluating SiFive RISC-V Core IP
Getting started with SiFive IP
This webinar is for embedded developers who are interested in learning more about the RISC-V architecture. Part 3 walks users through downloading and evaluating SiFive RISC-V Core IP, including E31 Evaluation RTL, and using Freedom Studio to program and debug code running on the E31 FPGA evaluation
Post Webinar Materials
Drew BarbierField Engineer at SiFive, Inc.
Drew has worked in the Semiconductor industry for over 10 years in various engineering and customer facing roles. At SiFive Drew is responsible for a variety of tasks including customer support, software and development tools, ecosystem development, documentation, and whatever makes the customer experience great.
SiFive was founded by the creators of the free and open RISC-V architecture as a reaction to the end of conventional transistor scaling and escalating chip design costs.