The SiFive Connect webinar series is designed to be highly educational and interactive, offering attendees a direct connection to industry experts. Each one-hour long webinar will take place twice on the same day – once at 9 a.m. PDT and again at 6 p.m. PDT enabling our global audience to choose the time that works best for them.
Hands-On with SiFive Software
This webinar series is designed to provide an in-depth look at SiFive's software offerings including Freedom E SDK, Freedom U SDK, Freedom Studio and Freedom Tools. Each webinar in this series will dive into the technical aspects of these offerings, and include a demo that is specifically designed to help users get started.
On Demand Webinars
SiFive USB 3.2 IP Solutions Including Retimer for High-Speed Consumer Applications
Mastering the art of embedded development with SiFive Freedom Studio
SiFive HBM2E IP Subsystem
SiFive Insight: A Comprehensive Debug and Trace Solution for RISC-V ISA
SiFive High-Bandwidth Memory (HBM2E) IP Subsystem
SiFive HBM2/2E IP Subsystem - Features and Implementation Guidelines
Rapid Embedded Prototyping with SiFive Software
Join us for a one-hour webinar to learn how to develop embedded software for RISC-V processors using the SiFive Freedom E SDK. We will review the environment dependencies, architecture, and implementation of the software and the processor-agnostic APIs. Based on an understanding of this, we will set up a development environment, compile, debug and run some benchmarks on a RISC-V processor.
Embedding Intelligence Everywhere with SiFive 7 Series Core IP
As we move from the Internet of Things to the “Intelligence of Things,” compute platforms need to scale and be power efficient in order to cater to the entire spectrum of applications. In this one-hour webinar, we will see how the SiFive 7 Series Cores can enable several vertical markets and how its architecture scales across different needs.
Getting Started with SiFive’s SoC IPs
Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud
Interlaken chip-to-chip connectivity IP has been used for many years in networking and switching fabrics to move high throughput data between large chips. With advanced technology nodes, increasing chip sizes and CPU cluster-based designs, Interlaken has found a unique spot as the protocol of choice for low latency, high throughput chip-to-chip connectivity. SiFive is extending its 8th generation of Interlaken IP with the introduction of Interlaken-Low Latency (LL) IP, which will enable low latency chip-to-chip connectivity in HPC, AI/ML, enterprise and cloud applications. Interlaken-LL IP can provide up to 256Gbps of reliable and scalable throughput between two chips; whereas the standard Interlaken IP from SiFive provides throughput of up to 1.2Tbps.