Introducing the U54-MC RISC-V Core IP – The First RISC-V Core with Linux Support

Since we launched the industry’s first open-source RISC-V SoC back in July of last year, we’ve had the pleasure of pushing the boundaries of the RISC-V ecosystem and have been delighted by the support that SiFive – and RISC-V – has gained from system designers and Makers alike.

Today, we are proud to announce we have taken the next step in our journey to deliver custom silicon to everyone who needs it. Introducing the U54-MC RISC-V Core IP, the industry’s first RISC-V based, 64-bit, quad-core application processor with support for full featured operating systems including Linux, Unix and FreeBSD.

The standard U54-MC RISC-V Core contains four U54 CPUs along with a single E51 CPU, and is the first RISC-V Core to include multicore support and cache coherence. Each U54 CPU utilizes a highly efficient five-stage in-order pipeline. The U54 cores support the RV64GC ISA, which is expected to be the standard for Linux-based RISC-V devices. The 64-bit E51 CPU serves as a management core and is fully coherent with the main U54 cores. The U54-MC RISC-V Core is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways, and smart IoT devices.

A development board based on U54-MC RISC-V Core IP will be available by Q1 2018.

The U54-MC RISC-V Core can be accessed at https://www.sifive.com/cores/u54-mc.

Please visit our RISC-V Core IP page to learn more about the U-Series.