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SiFive Blog

The latest insights, and deeper technology dives, from RISC-V leaders

The SiFive blog is your go-to-source for updates on all things RISC-V including processor IP, chip architecture, software and other innovations. Whether you’re producing the next great consumer device, optimizing a datacenter or building next-generation autos check back often to hear the latest from our experts.

You Will Not Get Fired for Choosing RISC-V

You Will Not Get Fired for Choosing RISC-V

Camille Kokozaki
Dec 27, 2018
Published by SemiWiki. These were the closing words Yunsup Lee, CTO, SiFive used at one of the December RISC-V Summit Keynotes entitled ‘Opportunities and Challenges of Building Silicon in the Cloud’. Fired up was more the mood among the 1000+ attendees of the RISC-V Summit held at the Santa Clara C...
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Getting Started with Zephyr RTOS v1.13.0 On RISC-V

Getting Started with Zephyr RTOS v1.13.0 On RISC-V

Oct 30, 2018
Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm excited to tell you about the most recent release of Zephyr RTOS, version 1.13.0! Zephyr RTOS is a real-time operating system hosted by The Linux Foundation, featuring support for a myriad of different platforms, architect...
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An Open Source Release of the Freedom U540-C000's Bootloader

Troy Benjegerdes
Sep 06, 2018
The FU540-C000, which is available on the HiFive Unleashed development board, is a Linux capable board based on the open source Freedom platform. We built this chip to drive RISC-V Linux development, and it's been incredibly successful. In the three months since we started shipping the board the R...
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Interrupts on the SiFive E2 Series

Drew Barbier | Senior Director of Product Marketing
Jul 12, 2018
Last week SiFive launched the new E2 Series RISC-V Core IP. The E2 Series represents SiFive’s smallest, most efficient Core IP Series and is targeted specifically for embedded microcontroller designs. One of the reasons it is great for microcontroller applications is because of its extremely small a...
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Intel Capital Investment Boosts Vision for the Future

Naveed Sherwani | Chief Executive Officer at SiFive
May 08, 2018
We’re very happy to announce that Intel Capital participated in our recent Series C funding round. The investment was revealed at the Intel Capital Global Summit earlier today. Now, you may be thinking, “$50.6 million provides immense potential for SiFive – so now what?” For those of you who aren’t ...
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RISC-V QEMU Part 2: The RISC-V QEMU port is upstream

Michael Clark
Apr 25, 2018
QEMU 2.12.0 was released on April 24th 2018 and this version is the first official QEMU version to contain the RISC-V port. This is yet another milestone towards the development of the Open Source RISC-V tools on top of the recent acceptance of RISC-V in Linux kernel 4.15 in December last year and G...
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