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SiFive Blog

The latest insights, and deeper technology dives, from RISC-V leaders

The SiFive blog is your go-to-source for updates on all things RISC-V including processor IP, chip architecture, software and other innovations. Whether you’re producing the next great consumer device, optimizing a datacenter or building next-generation autos check back often to hear the latest from our experts.

The First Leg of our Global Symposiums is a Wrap, and it was an Enormous Success!

The First Leg of our Global Symposiums is a Wrap, and it was an Enormous Success!

Mar 13, 2019
We welcomed over 600 attendees to the SiFive Tech Symposiums in Austin, Mountain View and Boston. The feedback we received is flattering. We heard comments like, “You guys are going bold, and we love it!” and “SiFive has built a solid team with good breadth of business and technology expertise,” and...
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The RISC-V Revolution is Going Global

This Month, you can join SiFive in Austin, Mountain View, or Boston

Feb 21, 2019
In 2018, we hosted several RISC-V technology symposia in India, China and Israel. These events were very successful in fueling the growing momentum surrounding the RISC-V ISA in these countries. It turns out that these events were just the tip of the iceberg. In 2019, SiFive is greatly expanding its...
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Embedded Intelligence Everywhere

Embedded Intelligence Everywhere

Jan 04, 2019
In 2018, we saw the rapid proliferation of the RISC-V architecture, with commercial deployments of SiFive Core IP in a broad range of applications ranging from wearables and edge devices to the enterprise core. Modern compute workloads are evolving rapidly and require the ability to scale performanc...
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You Will Not Get Fired for Choosing RISC-V

You Will Not Get Fired for Choosing RISC-V

Dec 27, 2018
Published by SemiWiki. These were the closing words Yunsup Lee, CTO, SiFive used at one of the December RISC-V Summit Keynotes entitled ‘Opportunities and Challenges of Building Silicon in the Cloud’. Fired up was more the mood among the 1000+ attendees of the RISC-V Summit held at the Santa Clara C...
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Open Standards Work!

Dec 18, 2018
We are really excited to see Wave Computing announce the open MIPS ISA and R6 processor core. SiFive would like to congratulate and welcome MIPS to the open-source community with its MIPS Open Initiative. The addition of the MIPS 32 and 64-bit open ISA will provide more options freely available to S...
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Getting Started with Zephyr RTOS v1.13.0 On RISC-V

Getting Started with Zephyr RTOS v1.13.0 On RISC-V

Oct 30, 2018
Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm excited to tell you about the most recent release of Zephyr RTOS, version 1.13.0! Zephyr RTOS is a real-time operating system hosted by The Linux Foundation, featuring support for a myriad of different platforms, architect...
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